Texas Instruments TMS320DM357 - Manual (Page 26)

3.1 USB Controller Peripheral Mode Operation
3.1.1 Peripheral Mode: Control Transactions
USB Controller Host and Peripheral Modes Operation www.ti.com
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Soft connect - After a reset, the SOFTCONN bit of POWER register (bit 6) is cleared to 0. The
controller will therefore appear disconnected until the software has set the SOFTCONN bit to 1. The
application software can then choose when to set the PHY into its normal mode. Systems with a
lengthy initialization procedure may use this to ensure that initialization is complete and the system is
ready to perform enumeration before connecting to the USB.
Once the SOFTCONN bit has been set, the software can also simulate a disconnect by clearing this bit
to 0.
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Entry into suspend mode
When operating as a peripheral device, the controller monitors activity on the bus and when no activity
has occurred for 3 ms, it goes into Suspend mode. If the Suspend interrupt has been enabled, an
interrupt will be generated at this time.
At this point, the controller can then be left active (and hence able to detect when Resume signaling
occurs on the USB), or the application may arrange to disable the controller by stopping its clock.
However, the controller will not then be able to detect Resume signaling on the USB. As a result, some
external hardware will be needed to detect Resume signaling (by monitoring the DM and DP signals),
so that the clock to the controller can be restarted.
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Resume Signaling - When resume signaling occurs on the bus, first the clock to the controller must be
restarted if necessary. Then the controller will automatically exit Suspend mode. If the Resume
interrupt is enabled, an interrupt will be generated.
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Initiating a remote wakeup - If the software wants to initiate a remote wakeup while the controller is in
Suspend mode, it should write to the Power register to set the RESUME bit to 1. The software should
leave then this bit set for approximately 10 ms (minimum of 2 ms, a maximum of 15 ms) before
resetting it to 0.
Note: No resume interrupt will be generated when the software initiates a remote wakeup.
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Reset Signaling - When reset signaling occurs on the bus, the controller will perform the following
actions:
– Sets FADDR register to 0
– Sets INDEX register to 0
– Flushes all endpoint FIFOs
– Clears all control/status registers
– Generates a reset interrupt.
If the HSENA bit in the POWER register (bit 5) was set, the controller also tries to negotiate for
high-speed operation.
Whether high-speed operation is selected is indicated by HSMODE bit of POWER register (bit 4).
When the application software receives a reset interrupt, it should close any open pipes and wait for
bus enumeration to begin.
Endpoint 0 is the main control endpoint of the core. The software is required to handle all the standard
device requests that may be sent or received via endpoint 0. These are described in Universal Serial Bus
Specification, Revision 2.0, Chapter 9. The protocol for these device requests involves different numbers
and types of transactions per transfer. To accommodate this, the software needs to take a state machine
approach to command decoding and handling.
The Standard Device Requests received by a USB peripheral device can be divided into three categories:
Zero Data Requests (in which all the information is included in the command), Write Requests (in which
the command will be followed by additional data), and Read Requests (in which the device is required to
send data back to the host).
This section looks at the sequence of actions that the software must perform to process these different
types of device request.
26 Universal Serial Bus (USB) Controller SPRUGH3 – November 2008
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