Texas Instruments TMS320DM357 - Manual (Page 135)

4.74 Transmit and Receive FIFO Register for Endpoint 1 (FIFO1)
4.75 Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)
www.ti.com Registers
The Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) is shown in Figure 89 and described in
Table 90 .
Figure 89. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1)
31 0
DATA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 90. Transmit and Receive FIFO Register for Endpoint 1 (FIFO1) Field Descriptions
Bit Field Value Description
31-0 DATA 0-FFFF FFFF Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint.
Reading from these addresses unloads data from the Receive FIFO for the corresponding
endpoint.
The Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) is shown in Figure 90 and described in
Table 91 .
Figure 90. Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)
31 0
DATA
R/W-0
LEGEND: R/W = Read/Write; -n = value after reset
Table 91. Transmit and Receive FIFO Register for Endpoint 2 (FIFO2) Field Descriptions
Bit Field Value Description
31-0 DATA 0-FFFF FFFFh Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint.
Reading from these addresses unloads data from the Receive FIFO for the corresponding
endpoint.
SPRUGH3 – November 2008 Universal Serial Bus (USB) Controller 135
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