beautypg.com

8 dma teardown procedure, 4 interrupt handling, Handling – Texas Instruments TMS320DM357 User Manual

Page 68: Controller, Conditions

background image

3.3.2.8

DMA Teardown Procedure

3.4

Interrupt Handling

USB Controller Host and Peripheral Modes Operation

www.ti.com

If RXn_AUTOREQ (where n is the channel number) of AUTOREQ register is set with binary 11, IN tokens
will be generated and sent to the target USB peripheral device even after the End Of DMA Packet is
reached. This feature is useful to keep data reception operational across multiple DMA packets in a Rx
queue. The host processor does not have to restart sending IN tokens for every DMA packet in the Rx
queue.

Transparent Mode Setup

Transparent receive DMA configuration is identical to RNDIS DMA configuration with the exception of the
following:

Each packet is defined by a single buffer descriptor with SOP and EOP bit fields set.

Packet size is not bounded to be a multiple of 64 byte but by max packet size.

CTRLR.RNDIS bit field should be cleared to zero.

RXn:AUTOREQ register field is programmed with the value of 0, which is programmed for no Auto
Request.

In order to Teardown a TX channel, the endpoint FIFO must be flushed after the DMA Teardown
completes. Teardown is not complete until the following steps are successfully completed.

Write the TX Teardown register in the CPPI DMA with the channel to teardown. The DMA will interrupt
after the teardown is complete and the TX Completion Pointer will be FFFF FFFCh. This indicates that
the DMA has completed the teardown and all of the associated CPPI buffers can be reclaimed.

Call the flush_tx_fifo routine (code provided in

Example 4

) once if the FIFO is set up for single-buffer or

twice for double-buffer.

Table 14

lists the interrupts generated by the USB controller.

Table 14. Interrupts Generated by the USB Controller

Interrupt

Description

Tx Endpoint [4:0]

Tx endpoint ready or error condition. For endpoints 4 to 0. (Rx and Tx for endpoint 0)

Rx Endpoint [4:1]

Rx endpoint ready or error condition. For endpoints 4 to 1. (Endpoint 0 has interrupt status in
Tx interrupt)

USB Core[8:0]

Interrupts for 9 USB conditions

DMA Tx Completion [3:0]

Tx DMA completion interrupt for channel 3 to 0

DMA Rx Completion [3:0]

Rx DMA completion interrupt for channel 3 to 0

Whenever any of these interrupt conditions are generated, the host processor is interrupted. The software
needs to read the different interrupt status registers (discussed in later section) to determine the source of
the interrupt.

The nine USB interrupt conditions are listed in

Table 15

.

Table 15. USB Interrupt Conditions

Interrupt

Description

USB[8]

DRVVBUS level change

USB[7]

VBus voltage < VBus Valid Threshold (VBus error)

USB[6]

SRP detected

USB[5]

Device Disconnected (Valid in Host Mode)

USB[4]

Device Connected (Valid in Host Mode)

68

Universal Serial Bus (USB) Controller

SPRUGH3 – November 2008

Submit Documentation Feedback