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Section 4.62 – Texas Instruments TMS320DM357 User Manual

Page 125

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4.62 Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)

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Registers

The Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR) is shown in

Figure 77

and

described in

Table 78

.

Figure 77. Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)

15

14

13

12

11

10

8

Reserved

ISO

DMAEN

DISNYET

DMAMODE

Reserved

R-0

R/W-0

R/W-0

R/W-0

R/W-0

R-0

7

6

5

4

3

2

1

0

CLRDATATOG

SENTSTALL

SENDSTALL

FLUSHFIFO

DATAERROR

OVERRUN

FIFOFULL

RXPKTRDY

W-0

R/W-0

R/W-0

W-0

R-0

R/W-0

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; W = Write only; -n = value after reset

Table 78. Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)

Field Descriptions

Bit

Field

Value

Description

15

Reserved

0

Reserved

14

ISO

0-1

Set this bit to enable the Receive endpoint for Isochronous transfers, and clear this bit to enable the
Receive endpoint for Bulk/Interrupt transfers.

13

DMAEN

0-1

Set this bit to enable the DMA request for the Receive endpoints.

12

DISNYET

0-1

Set this bit to disable the sending of NYET handshakes. When set, all successfully received
Receive packets are ACKed, including at the point at which the FIFO becomes full.

Note: This bit only has any effect in high-speed mode, in which mode it should be set for all
Interrupt endpoints.

11

DMAMODE

0

This bit should always be cleared to 0.

10-8

Reserved

0

Reserved

7

CLRDATATOG

0-1

Set this bit to reset the endpoint data toggle to 0.

6

SENTSTALL

0-1

This bit is set when a STALL handshake is transmitted. The FIFO is flushed and the TXPKTRDY bit
is cleared. You should clear this bit.

5

SENDSTALL

0-1

Set this bit to issue a STALL handshake. Clear this bit to terminate the stall condition.

Note: This bit has no effect where the endpoint is being used for Isochronous transfers.

4

FLUSHFIFO

0-1

Set this bit to flush the next packet to be read from the endpoint Receive FIFO. The FIFO pointer is
reset and the RXPKTRDY bit is cleared.

Note: FLUSHFIFO has no effect unless RXPKTRDY is set. Also note that, if the FIFO is
double-buffered, FLUSHFIFO may need to be set twice to completely clear the FIFO.

3

DATAERROR

0-1

This bit is set when RXPKTRDY is set if the data packet has a CRC or bit-stuff error. It is cleared
when RXPKTRDY is cleared.

Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always
returns zero.

2

OVERRUN

0-1

This bit is set if an OUT packet cannot be loaded into the Receive FIFO. You should clear this bit.

Note: This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always
returns zero.

1

FIFOFULL

0-1

This bit is set when no more packets can be loaded into the Receive FIFO.

0

RXPKTRDY

0-1

This bit is set when a data packet has been received. You should clear this bit when the packet has
been unloaded from the Receive FIFO. An interrupt is generated when the bit is set.

SPRUGH3 – November 2008

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