Texas Instruments TMS320DM357 - Manual (Page 38)

3.1.2.2 Peripheral Mode: Bulk OUT Transactions
USB Controller Host and Peripheral Modes Operation www.ti.com
3.1.2.1.2 Operation
When data is to be transferred over a Bulk IN pipe, a data packet needs to be loaded into the FIFO and
the PERI_TXCSR register written to set the TXPKTRDY bit (bit 0). When the packet has been sent, the
TXPKTRDY bit will be cleared by the USB controller and an interrupt generated so that the next packet
can be loaded into the FIFO. If double packet buffering is enabled, then after the first packet has been
loaded and the TXPKTRDY bit set, the TXPKTRDY bit will immediately be cleared by the USB controller
and an interrupt generated so that a second packet can be loaded into the FIFO. The software should
operate in the same way, loading a packet when it receives an interrupt, regardless of whether double
packet buffering is enabled or not.
In the general case, the packet size must not exceed the size specified by the lower 11 bits of the
TXMAXP register. This part of the register defines the payload (packet size) for transfers over the USB
and is required by the USB Specification to be either 8, 16, 32, 64 (Full-Speed or High-Speed) or 512
bytes (High-Speed only).
The host may determine that all the data for a transfer has been sent by knowing the total amount of data
that is expected. Alternatively it may infer that all the data has been sent when it receives a packet which
is smaller than the stated payload (TXMAXP [bit 10 : bit 0]). In the latter case, if the total size of the data
block is a multiple of this payload, it will be necessary for the function to send a null packet after all the
data has been sent. This is done by setting TXPKTRDY when the next interrupt is received, without
loading any data into the FIFO.
If large blocks of data are being transferred, then the overhead of calling an interrupt service routine to
load each packet can be avoided by using DMA.
3.1.2.1.3 Error Handling
If the software wants to shut down the Bulk IN pipe, it should set the SENDSTALL bit (bit 4 of
PERI_TXCSR). When the controller receives the next IN token, it will send a STALL to the host, set the
SENTSTALL bit (bit 5 of PERI_TXCSR) and generate an interrupt.
When the software receives an interrupt with the SENTSTALL bit (bit 5 of PERI_TXCSR) set, it should
clear the SENTSTALL bit. It should however leave the SENDSTALL bit set until it is ready to re-enable the
Bulk IN pipe.
Note: If the host failed to receive the STALL packet for some reason, it will send another IN token,
so it is advisable to leave the SENDSTALL bit set until the software is ready to re-enable the
Bulk IN pipe. When a pipe is re-enabled, the data toggle sequence should be restarted by
setting the CLRDATATOG bit in the PERI_TXCSR register (bit 6).
A Bulk OUT transaction is used to transfer non-periodic data from the host to the function controller.
The following optional features are available for use with an Rx endpoint used in peripheral mode for Bulk
OUT transactions:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO on reception
from the host. Double packet buffering is enabled by setting the DPB bit of the RXFIFOSZ register (bit
4).
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint has
a packet in its FIFO. This feature can be used to allow the DMA controller to unload packets from the
FIFO without processor intervention.
When DMA is enabled, endpoint interrupt will not be generated for completion of packet reception.
Endpoint interrupt will be generated only in the error conditions.
38 Universal Serial Bus (USB) Controller SPRUGH3 – November 2008
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