6 reset considerations, 1 software reset considerations, 2 hardware reset considerations – Texas Instruments TMS320DM357 User Manual
Page 74: 3 usb reset considerations, 7 interrupt support, 8 edma event support, 9 power management, Considerations, Support, Management
3.6
Reset Considerations
3.6.1
Software Reset Considerations
3.6.2
Hardware Reset Considerations
3.6.3
USB Reset Considerations
3.7
Interrupt Support
3.8
EDMA Event Support
3.9
Power Management
USB Controller Host and Peripheral Modes Operation
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The USB controller has two reset sources: hardware reset and the soft reset (RESET bit in CTRLR
register).
When the RESET bit in CTRLR is set, all the USB controller registers and DMA operations are reset. The
bit is cleared automatically.
A software reset on the ARM or DSP CPUs does not affect the register values and operation of the USB
controller.
When a hardware reset is asserted, all the registers are set to their default values.
When operating in peripheral mode, a USB reset received from the host causes some internal registers to
be reset. The USB controller setup operations (for example FIFO sizing) in peripheral mode should be
performed after receiving the USB reset, and again on each subsequent USB reset. There are some
conditions where multiple USB reset interrupts may be received in rapid succession. Good interrupt
handling practices must be observed to assure that the setup is performed (again) after the final USB
reset interrupt.
Software must teardown any TX DMA channel use upon receipt of a USB reset. See
.
The USB peripheral presents a single interrupt to the ARM interrupt controller (AINTC). For information on
the mapping of interrupts, refer to the device-specific data manual.
The USB is an internal bus master peripheral and therefore does not utilize any EDMA events. The
registers support only individual access. Bursting data to or from the USB register space through EDMA is
not supported.
The USB controller can be placed in reduced power modes to conserve power during periods of low
activity. The power management of the peripheral is controlled by the processor Power and Sleep
Controller (PSC). The PSC acts as a master controller for power management for all of the peripherals on
the device. For detailed information on power management procedures using the PSC, see the
TMS320DMxxx DMSoC ARM Subsystem Reference Guide (spru856).
74
Universal Serial Bus (USB) Controller
SPRUGH3 – November 2008