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Section 4.76, Section 4.77 – Texas Instruments TMS320DM357 User Manual

Page 136

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4.76 Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)

4.77 Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)

Registers

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The Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) is shown in

Figure 91

and described in

Table 92

.

Figure 91. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3)

31

0

DATA

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 92. Transmit and Receive FIFO Register for Endpoint 3 (FIFO3) Field Descriptions

Bit

Field

Value

Description

31-0

DATA

0-FFFF FFFFh

Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint.

Reading from these addresses unloads data from the Receive FIFO for the corresponding
endpoint.

The Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) is shown in

Figure 92

and described in

Table 93

.

Figure 92. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4)

31

0

DATA

R/W-0

LEGEND: R/W = Read/Write; -n = value after reset

Table 93. Transmit and Receive FIFO Register for Endpoint 4 (FIFO4) Field Descriptions

Bit

Field

Value

Description

31-0

DATA

0-FFFF FFFFh

Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint.

Reading from these addresses unloads data from the Receive FIFO for the corresponding
endpoint.

Universal Serial Bus (USB) Controller

136

SPRUGH3 – November 2008

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