Texas Instruments TMS320DM357 - Manual (Page 37)

3.1.2 Bulk Transactions
3.1.2.1 Peripheral Mode: Bulk In Transactions
www.ti.com USB Controller Host and Peripheral Modes Operation
A Bulk IN transaction is used to transfer non-periodic data from the USB peripheral device to the host.
The following optional features are available for use with a Tx endpoint used in peripheral mode for Bulk
IN transactions:
•
Double packet buffering: When enabled, up to two packets can be stored in the FIFO awaiting
transmission to the host. Double packet buffering is enabled by setting the DPB bit of TXFIFOSZ
register (bit 4).
•
DMA: If DMA is enabled for the endpoint, a DMA request will be generated whenever the endpoint is
able to accept another packet in its FIFO. This feature allows the DMA controller to load packets into
the FIFO without processor intervention.
When DMA is enabled and DMAMODE bit of PERI_TXCSR is set, an endpoint interrupt is not
generated for completion of the packet transfer. An endpoint interrupt is generated only in the error
conditions.
3.1.2.1.1 Setup
In configuring a TX endpoint for bulk transactions, the TXMAXP register must be written with the
maximum packet size (in bytes) for the endpoint. This value should be the same as the wMaxPacketSize
field of the Standard Endpoint Descriptor for the endpoint and the PERI_TXCSR register should be set as
shown in
Table 2 :
Table 2. PERI_TXCSR Register Bit Configuration for Bulk IN Transactions
Bit Position Bit Field Name Configuration
Bit 14 ISO Cleared to 0 for bulk mode operation
Bit 13 MODE Set to 1 to make sure the FIFO is enabled (only necessary if the FIFO is shared with an RX
endpoint)
Bit 12 DMAEN Set to 1 if DMA requests must be enabled
Bit 11 FRCDATATOG Cleared to 0 to allow normal data toggle operations
Bit 10 DMAMODE Set to 1 when DMA is enabled and EP interrupt is not needed for each packet transmission
When the endpoint is first configured (following a SET_CONFIGURATION or SET_INTERFACE command
on Endpoint 0), the lower byte of PERI_TXCSR should be written to set the CLRDATATOG bit (bit 6). This
will ensure that the data toggle (which is handled automatically by the controller) starts in the correct state.
Also if there are any data packets in the FIFO (indicated by the FIFONOTEMPTY bit (bit 1 of
PERI_TXCSR) being set), they should be flushed by setting the FLUSHFIFO bit (bit 3 of PERI_TXCSR).
Note: It may be necessary to set this bit twice in succession if double buffering is enabled.
SPRUGH3 – November 2008 Universal Serial Bus (USB) Controller 37
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