Sharp SF-1120 - Manual (Page 124)

4 Internal block diagram
PS3/A19
PS2/A18
PS1/A17
PS0/A16
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
P95/SCK1/IRQ5
P94/SCK0/IRQ4
P93/RXD1
P92/RXD0
P91/TXD1
P90/TXD0
Vc
c
Vs
s
P
37/D
1
5
P
36/D
1
4
P
35/D
1
3
P
34/D
1
2
P
33/D
1
1
P
32/D
1
0
P
31/D
9
P
30/D
8
P
47/D
7
P
46/D
6
P
45/D
5
P
44/D
4
P
43/D
3
P
42/D
2
P
41/D
1
P
40/D
0
Vs
s
Vs
s
Vs
s
Vs
s
Vs
s
Vc
c
Vc
c
MD2
MD1
MD0
EXTAL
XTAL
STBY
RES
RES0
NMI
P66/LWR
P65/HWR
P64/RD
P63/AS
P62/BACK
P61/BREQ
P60/WAIT
P84/CS0
P83/CS1/IRQ3
P82/CS2/IRQ2
P81/CS3/IRQ1
P80/RFSH/IRQ0
Φ
RAM
PB7
/T
P1
5
/D
R
EQ
1
/AD
TR
G
PB6
/T
P1
4
/D
R
E
Q
0
PB5
/T
P1
3
/TO
C
XB4
PB4
/T
P1
2
/TO
C
XA4
PB3
/T
P1
1
/TI
O
C
A4
PB2
/T
P1
0
/TI
O
C
B4
P
B
1
/T
P
9
/T
IO
C
B
3
P
B
0
/T
P
8
/T
IO
C
A
3
PA7
/T
P7
/T
IO
C
B
2
/A2
0
PA6
/T
P6
/T
IO
C
A
2
/A2
1
PA5
/T
P5
/T
IO
C
B
1
/A2
2
PA4
/T
P4
/T
IO
C
A
1
/A2
3
P
A
3
/T
P
3
/T
IO
C
B
0/T
C
LK
D
P
A
2
/T
P
2
/T
IO
C
A
0/T
C
LK
C
PA1
/T
P1
/T
EN
D
1
/T
C
L
KB
PA0
/T
P0
/T
EN
D
0
/T
C
L
KA
A Vc
c
A Vs
s
Vre
f
P7
7
/AN
7
/D
A
1
P7
6
/AN
6
/D
A
0
P
75/A
N
5
P
74/A
N
4
P
73/A
N
3
P
72/A
N
2
P
71/A
N
1
P
70/A
N
0
H8/3042
H8/3041
H8/3040 64KByte
48KByte
32KByte
HS/300H CPU
*ROM capacity
Port 3 Port 4
Address bus
Address bus (Upper)
Address bus (Lower)
Cl
o
c
k
o
s
c
illa
to
r
Interruption
controller
DMA
contorller
(DMAC)
B
u
s
c
ontol
le
r
Por
t 6
Po
rt
8
ROM*
(Mask ROM)
Refresh
controller
16-bit integrated
timer pulse unit
(ITU)
Watchdog timer
serial communication
interface
(SCI) x 2ch
Programmable
timing pattern
controller (TPC)
A/D convertor
D/A convertor
Port B Port A Port 7
P
o
rt
9
P
or
t 1
P
or
t 2
P
or
t
5
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