Maxim Integrated DS33R11 - Manual (Page 2)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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TABLE OF CONTENTS
1 DESCRIPTION ................................................................................................................................... 9
2 FEATURE HIGHLIGHTS.................................................................................................................. 11
2.1 G ENERAL ...................................................................................................................................... 11
2.2 M ICROPROCESSOR I NTERFACE ...................................................................................................... 11
2.3 HDLC E THERNET M APPING .......................................................................................................... 11
2.4 X.86 (L INK A CCESS P ROTOCOL FOR SONET/SDH) E THERNET M APPING ....................................... 11
2.5 A DDITIONAL HDLC C ONTROLLERS IN THE I NTEGRATED T1/E1/J1 T RANSCEIVER ............................ 12
2.6 C OMMITTED I NFORMATION R ATE (CIR) C ONTROLLER .................................................................... 12
2.7 SDRAM I NTERFACE ...................................................................................................................... 12
2.8 MAC I NTERFACE ........................................................................................................................... 12
2.9 T1/E1/J1 L INE I NTERFACE ............................................................................................................ 13
2.10 C LOCK S YNTHESIZER .................................................................................................................... 13
2.11 J ITTER A TTENUATOR ..................................................................................................................... 13
2.12 T1/E1/J1 F RAMER ........................................................................................................................ 14
2.13 TDM B US ..................................................................................................................................... 14
2.14 T EST AND D IAGNOSTICS ................................................................................................................ 15
2.15 S PECIFICATIONS C OMPLIANCE ....................................................................................................... 16
3 APPLICATIONS ............................................................................................................................... 17
4 ACRONYMS AND GLOSSARY ....................................................................................................... 18
5 MAJOR OPERATING MODES ........................................................................................................ 19
6 BLOCK DIAGRAMS......................................................................................................................... 20
7 PIN DESCRIPTIONS........................................................................................................................ 25
7.1 P IN F UNCTIONAL D ESCRIPTION ...................................................................................................... 25
8 FUNCTIONAL DESCRIPTION ......................................................................................................... 41
8.1 P ROCESSOR I NTERFACE ............................................................................................................... 42
8.1.1 Read-Write/Data Strobe Modes............................................................................................................42
8.1.2 Clear on Read .......................................................................................................................................42
8.1.3 Interrupt and Pin Modes........................................................................................................................42
9 ETHERNET MAPPER ...................................................................................................................... 43
9.1 E THERNET M APPER C LOCKS ......................................................................................................... 43
9.1.1 Ethernet Interface Clock Modes............................................................................................................45
9.1.2 Serial Interface Clock Modes ................................................................................................................45
9.2 R ESETS AND L OW P OWER M ODES ................................................................................................. 46
9.3 I NITIALIZATION AND C ONFIGURATION .............................................................................................. 47
9.4 G LOBAL R ESOURCES .................................................................................................................... 47
9.5 P ER -P ORT R ESOURCES ................................................................................................................ 47
9.6 D EVICE I NTERRUPTS ..................................................................................................................... 48
9.7 I NTERRUPT I NFORMATION R EGISTERS ........................................................................................... 50
9.8 S TATUS R EGISTERS ...................................................................................................................... 50
9.9 I NFORMATION R EGISTERS ............................................................................................................. 50
9.10 S ERIAL I NTERFACE ........................................................................................................................ 50
9.11 C ONNECTIONS AND Q UEUES ......................................................................................................... 51
9.12 A RBITER ....................................................................................................................................... 52
9.13 F LOW C ONTROL ............................................................................................................................ 53
9.13.1 Full Duplex Flow Control.......................................................................................................................54
9.13.2 Half Duplex Flow Control ......................................................................................................................55
9.13.3 Host-Managed Flow Control .................................................................................................................55
9.14 E THERNET I NTERFACE P ORT ......................................................................................................... 56