Figure 13-13. receive-side timing – Maxim Integrated DS33R11 User Manual
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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
328 of 344
Figure 13-13. Receive-Side Timing
tD1
1
tD2
RSERO / RDATA / RSIG
RCHCLK
RCHBLK
RSYNC
RCLKO
RFSYNC / RMSYNC
tD2
tD2
tD2
1ST FRAME BIT
NOTE 1: RSYNC IS IN THE OUTPUT MODE.
NOTE 2: NO RELATIONSHIP BETWEEN RCHCLK AND RCHBLK AND OTHER SIGNALS IS IMPLIED.