beautypg.com

Maxim Integrated DS33R11 User Manual

Page 290

background image

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

290 of 344

Register Name:

TR.TSACR

Register Description:

Transmit Sa Bit Control Register

Register Address:

DAh


Bit

# 7 6 5 4 3 2 1 0

Name SiAF

SiNAF RA Sa4 Sa5 Sa6 Sa7 Sa8

Default

0 0 0 0 0 0 0 0


Bit 7: International Bit in Align Frame Insertion Control Bit (SiAF)

0 = do not insert data from the TR.TSiAF register into the transmit data stream
1 = insert data from the TR.TSiAF register into the transmit data stream


Bit 6: International Bit in Nonalign Frame Insertion Control Bit (SiNAF)

0 = do not insert data from the TR.TSiNAF register into the transmit data stream
1 = insert data from the TR.TSiNAF register into the transmit data stream


Bit 5: Remote Alarm Insertion Control Bit (RA)

0 = do not insert data from the TR.TRA register into the transmit data stream
1 = insert data from the TR.TRA register into the transmit data stream


Bit 4: Additional Bit 4 Insertion Control Bit (Sa4)

0 = do not insert data from the TR.TSa4 register into the transmit data stream
1 = insert data from the TR.TSa4 register into the transmit data stream


Bit 3: Additional Bit 5 Insertion Control Bit (Sa5)

0 = do not insert data from the TR.TSa5 register into the transmit data stream
1 = insert data from the TR.TSa5 register into the transmit data stream


Bit 2: Additional Bit 6 Insertion Control Bit (Sa6)

0 = do not insert data from the TR.TSa6 register into the transmit data stream
1 = insert data from the TR.TSa6 register into the transmit data stream

Bit 1: Additional Bit 7 Insertion Control Bit (Sa7)

0 = do not insert data from the TR.TSa7 register into the transmit data stream
1 = insert data from the TR.TSa7 register into the transmit data stream


Bit 0: Additional Bit 8 Insertion Control Bit (Sa8)

0 = do not insert data from the TR.TSa8 register into the transmit data stream
1 = insert data from the TR.TSa8 register into the transmit data stream


Register Name:

TR.BAWC

Register Description:

BERT Alternating Word-Count Rate

Register Address:

DBh

Bit

# 7 6 5 4 3 2 1 0

Name ACNT7 ACNT6 ACNT5 ACNT4 ACNT3 ACNT2 ACNT1 ACNT0
Default

0 0 0 0 0 0 0 0


Bits 0 – 7: Alternating Word-Count Rate Bits 0 to 7 (ACNT0 to ACNT7). ACNT0 is the LSB of the 8-bit
alternating word-count rate counter.