Maxim Integrated DS33R11 - Manual (Page 196)

DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
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Register Name:
SU.TxFrmCtr
Register Description: MAC All Frames Transmitted Counter
Register Address: 0300h (indirect)
0300h:
Bit
# 31 30 29 28 27 26 25 24
Name TXFRMC31 TXFRMC30 TXFRMC29 TXFRMC28 TXFRMC27 TXFRMC26 TXFRMC25 TXFRMC24
Default 0 0 0 0 0 0 0 0
0301h:
Bit
# 23 22 21 20 19 18 17 16
Name TXFRMC23 TXFRMC22 TXFRMC21 TXFRMC20 TXFRMC19 TXFRMC18 TXFRMC17 TXFRMC16
Default 0 0 0 0 0 0 0 0
0302h:
Bit
# 15 14 13 12 11 10 09 08
Name TXFRMC15 TXFRMC14 TXFRMC13 TXFRMC12 TXFRMC11 TXFRMC10 TXFRMC9 TXFRMC8
Default 0 0 0 0 0 0 0 0
0303h:
Bit
# 07 06 05 04 03 02 01 00
Name TXFRMC7 TXFRMC6 TXFRMC5 TXFRMC4 TXFRMC3 TXFRMC2 TXFRMC1 TXFRMC0
Default 0 0 0 0 0 0 0 0
Bits 0 - 31: All Frames Transmitted Counter (TXFRMC[0:31]) 32 bit value indicating the number of frames
transmitted. Each time a frame is transmitted, this counter is incremented by 1. This counter resets only upon
device reset, does not saturate, and rolls-over to zero upon reaching the maximum value. The user should ensure
that the measurement period is less than the minimum length of time required for the counter to increment 2^32-1
times at the maximum frame rate. The user should store the value from the beginning of the measurement period
for later calculations, and take into account the possibility of a roll-over to occurring.