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Maxim Integrated DS33R11 User Manual

Page 153

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DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver

153 of 344

Register Name:

LI.TIFGC

Register Description:

Transmit Inter-Frame Gapping Control Register

Register Address:

0C5h


Bit

# 7 6 5 4 3 2 1 0

Name TIFG7 TIFG6 TIFG5 TIFG4 TIFG3 TIFG2 TIFG1 TIFG0
Default

0 0 0 0 0 0 0 1


Bits 0 - 7: Transmit Inter-Frame Gapping (TIFG[7:0]) – These eight bits indicate the number of additional flags
and bytes of inter-frame fill to be inserted between packets. The number of flags and bytes of inter-frame fill
between packets is at least the value of TIFG[7:0] plus 1. Note: If inter-frame fill is set to all 1’s, a TFIG value of 2
or 3 will result in a flag, two bytes of 1’s, and an additional flag between packets.


Register Name:

LI.TEPLC

Register Description:

Transmit Errored Packet Low Control Register

Register Address:

0C6h


Bit

# 7 6 5 4 3 2 1 0

Name TPEN7 TPEN6 TPEN5 TPEN4 TPEN3 TPEN2 TPEN1 TPEN0
Default

0 0 0 0 0 0 0 0


Bits 0 – 7: Transmit Errored Packet Insertion Number (TPEN[7:0]) – These eight bits indicate the total number
of errored packets to be transmitted when triggered by TIAEI. Error insertion will end after this number of errored
packets have been transmitted. A value of FFh results in continuous errored packet insertion at the specified rate.