SMSC LAN91C111 Instruction Manuals and User Guides
We have 1 Instruction Manual and User Guide for LAN91C111 SMSC
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 128 |
| Size: | 1.36 MB |
Show table of contents
Document Outline
- Chapter 1 General Description
- Chapter 2 Pin Configurations
- Chapter 3 Block Diagrams
- Chapter 4 Signal Descriptions
- Chapter 5 Description of Pin Functions
- Chapter 6 Signal Description Parameters
- Chapter 7 Functional Description
- 7.1 Clock Generator Block
- 7.2 CSMA/CD Block
- 7.3 MMU Block
- 7.4 BIU Block
- 7.5 MAC-PHY Interface
- 7.6 Serial EEPROM Interface
- 7.7 Internal Physical Layer
- Figure 7.3 TX/10BT Frame Format
- 7.7.1 MII Disable
- 7.7.2 Encoder
- 7.7.3 Decoder
- 7.7.4 Clock and Data Recovery
- 7.7.5 Scrambler
- 7.7.6 Descrambler
- 7.7.7 Twisted Pair Transmitter
- 7.7.8 Twisted Pair Receiver
- 7.7.9 Collision
- 7.7.10 Start of Packet
- 7.7.11 End of Packet
- 7.7.12 Link Integrity & AutoNegotiation
- 7.7.13 Jabber
- 7.7.14 Receive Polarity Correction
- 7.7.15 Full Duplex Mode
- 7.7.16 Loopback
- 7.7.17 PHY Powerdown
- 7.7.18 PHY Interrupt
- 7.8 Reset
- Chapter 8 MAC Data Structures and Registers
- 8.1 Frame Format In Buffer Memory
- 8.2 Receive Frame Status
- 8.3 I/O Space
- 8.4 Bank Select Register
- 8.5 Bank 0 - Transmit Control Register
- 8.6 Bank 0 - EPH Status Register
- 8.7 Bank 0 - Receive Control Register
- 8.8 Bank 0 - Counter Register
- 8.9 Bank 0 - Memory Information Register
- 8.10 Bank 0 - Receive/Phy Control Register
- 8.11 Bank 1 - Configuration Register
- 8.12 Bank 1 - Base Address Register
- 8.13 Bank 1 - Individual Address Registers
- 8.14 Bank 1 - General Purpose Register
- 8.15 Bank 1 - Control Register
- 8.16 Bank 2 - MMU Command Register
- 8.17 Bank 2 - Packet Number Register
- 8.18 Bank 2 - FIFO Ports Register
- 8.19 Bank 2 - Pointer Register
- 8.20 Bank 2 - Data Register
- 8.21 Bank 2 - Interrupt Status Registers
- 8.22 Bank 3 - Multicast Table Registers
- 8.23 Bank 3 - Management Interface
- 8.24 Bank 3 - Revision Register
- 8.25 Bank 3 - RCV Register
- 8.26 Bank 7 - External Registers
- Chapter 9 PHY MII Registers
- Table 9.1 MII Serial Frame Structure
- Table 9.2 MII Serial Port Register MAP
- 9.1 Register 0. Control Register
- 9.2 Register 1. Status Register
- 9.3 Register 2&3. PHY Identifier Register
- 9.4 Register 4. Auto-Negotiation Advertisement Register
- 9.5 Register 5. Auto-Negotiation Remote End Capability Register
- 9.6 Register 16. Configuration 1- Structure and Bit Definition
- 9.7 Register 17. Configuration 2 - Structure and Bit Definition
- 9.8 Register 18. Status Output - Structure and Bit Definition
- 9.9 Register 19. Mask - Structure and Bit Definition
- 9.10 Register 20. Reserved - Structure and Bit Definition
- Chapter 10 Software Driver and Hardware Sequence Flow
- Chapter 11 Board Setup Information
- Chapter 12 Application Considerations
- Chapter 13 Operational Description
- Chapter 14 Timing Diagrams
- Figure 14.1 Asynchronous Cycle - nADS=0
- Figure 14.2 Asynchronous Cycle - Using nADS
- Figure 14.3 Asynchronous Cycle - nADS=0
- Figure 14.4 Asynchronous Ready
- Figure 14.5 Burst Write Cycles - nVLBUS=1
- Figure 14.6 Burst Read Cycles - nVLBUS=1
- Figure 14.7 Address Latching for All Modes
- Figure 14.8 Synchronous Write Cycle - nVLBUS=0
- Figure 14.9 Synchronous Read Cycle - nVLBUS=0
- Figure 14.10 MII Timing
- Table 14.1 Transmit Timing Characteristics
- Figure 14.11 Transmit Timing
- Table 14.2 Receive Timing Characteristics
- Figure 14.12 Receive Timing, End of Packet - 10 MBPS
- Table 14.3 Collision and Jam Timing Characteristics
- Figure 14.13 Collision Timing, Receive
- Figure 14.14 Collision Timing, Transmit
- Figure 14.15 Jam Timing
- Table 14.4 Link Pulse Timing Characteristics
- Figure 14.16 Link Pulse Timing
- Figure 14.17 FLP Link Pulse Timing
- Chapter 15 Package Outlines
- Chapter 16 Revision History