Avago Technologies LSI53C320 - Manual (Page 9)

Contents ix
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
Tables
1.1 Types of Operation 1-2
1.2 SCSI Bus Length Limits in a Clustering Configuration 1-4
1.3 SCSI Bus Length Limits 1-5
2.1 DIFFSENS Voltage Levels 2-8
2.2 Total Cable Length for Ultra320 SCSI Using the
LSI53C320
2-10
3.1 SCSI A Side Interface Signals 3-3
3.2 SCSI B Side Interface Signals 3-4
3.3 Chip Interface Control Signals 3-5
3.4 Serial EEPROM Signals 3-6
3.5 Power and Ground Pins 3-6
3.6 Test Signals for LSI Logic Only 3-7
4.1 Absolute Maximum Stress Ratings 4-1
4.2 Operating Conditions 4-2
4.3 LVD Driver SCSI Signals—SD[15:0]
±
, SDP[1:0]
±
,
SCD
±
, SIO
±
, SMSG
±
, SREQ
±
, SACK
±
, SBSY
±
,
SATN
±
, SSEL
±
, SRST
±
4-2
4.4 LVD Receiver SCSI Signals—SD[15:0]
±
, SDP[1:0]
±
,
SCD
±
, SIO
±
, SMSG
±
, SREQ
±
, SACK
±
, SBSY
±
,
SATN
±
, SSEL
±
, SRST
±
4-3
4.5 Bidirectional SCSI Signals—SD[15:0]/, SDP[1:0]/, SREQ/,
SACK/, SD[15:0]
±
, SDP[1:0]
±
, SREQ
±
, SACK
±
4-4
4.6 Bidirectional SCSI Control Signals—SCD/, SIO/, SMSG/,
SBSY/, SATN/, SSEL/, SRST/, SCD
±
, SIO
±
, SMSG
±
,
SBSY
±
, SATN
±
, SSEL
±
, SRST
±
4-4
4.7 DIFFSENS SCSI Signal 4-4
4.8 Input Capacitance 4-5
4.9 Input Control Signals—CLOCK, CHIP_RESET/,
WS_ENABLE/
4-5
4.10 Output Control Signals—BSY_LED, XFER_ACTIVE 4-5
4.11 TolerANT Technology Electrical Characteristics 4-6
4.12 Clock Timing 4-8