Avago Technologies LSI53C320 - Manual (Page 25)

Ultra320 SCSI Functional Description 2-7
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
2.2.1.5 Cyclic Redundancy Check (CRC)
Ultra320 SCSI and Ultra160 SCSI devices employ CRC as an error
detection code during the DT Data phases. The LSI53C320 handles
CRC as another data phase with the appropriate specific timing values.
2.2.1.6 LSI53C320 Requirements for Synchronous SCSI Negotiation
The LSI53C320 builds a table of information regarding devices on the
bus in on-chip RAM. The LSI53C320 reads the PPR, Synchronous Data
Transfer Request (SDTR), and Wide Data Transfer Request (WDTR)
information for each device from the MSG bytes during negotiation.
For devices to communicate accurately through the LSI53C320 at
Ultra320 SCSI rates, it is necessary for a complete asynchronous
negotiation to occur between the initiator and target(s) prior to any
synchronous data transfer. The LSI53C320 defaults to Ultra SCSI rates
when a valid negotiation between the initiator and target does not occur.
2.2.2 SCSI Bus Interface
This section describes the SCSI bus interfaces on the LSI53C320.
2.2.2.1 SCSI Bus Modes
To support greater device connectivity and longer SCSI cables, the
LSI53C320 features LVDlink technology, the LSI Logic implementation of
multimode LVD SCSI. The LVDlink transceivers can operate in the LVD
or SE modes.
The voltage levels on the A_DIFFSENS and B_DIFFSENS signals
determine the SCSI bus mode. The LSI53C320 DIFFSENS receivers
detect the voltage level on the A Side or B Side DIFFSENS lines
independently. The LSI53C320 does not change the present signal mode
until it continuously senses a new DIFFSENS voltage level for 100 ms.
Table 2.1 shows the voltages on the DIFFSENS lines.