Avago Technologies LSI53C320 - Manual (Page 68)

IX-2 Index
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
F
filter edges 2-13
functional signal grouping 3-2
H
high voltage differential 1-1
host B-1
host adapter B-1
I
I/O voltage 4-2
information unit 2-6
Initiator B-1
initiator B-1
input
capacitance 4-5
I/O pads 4-5
input pads 4-5
low voltage 4-4
voltage 4-1
input clock signals 2-15
input control signals
CLOCK, RESET/, WS_ENABLE/ 4-5
intersymbol interference 1-5
ISI 1-5
,
2-4
J
junction temperature 4-2
L
latch-up current 4-1
,
4-2
leading edge filter 2-11
,
2-12
LED 3-5
load bus 2-11
logical unit B-1
low voltage differential 1-1
LSI53C320
272-ball BGA (left half) 4-12
272-ball BGA (right half) 4-13
additional control capability 1-2
applications 1-3
clock 3-5
dynamic transmission mode 2-8
features 1-7
independent RBIAS pins 1-1
processing data 2-11
receiver logic 2-11
retiming logic 2-2
server clustering 1-3
LVD 2-8
,
B-1
driver SCSI signals 4-2
receiver SCSI signals 4-3
LVDlink 1-6
features 1-6
transceivers 1-6
,
2-7
M
master reset 3-5
maximum cable lengths 2-8
migration path 1-6
N
negation B-2
nexus 2-3
O
on-chip RAM 2-3
operating conditions 4-2
operating free air 4-2
output
low voltage 4-4
output control signals
BSY_LED, XFER_ACTIVE 4-5
P
P1 line 2-4
paced transfers 2-4
packetized protocol 2-6
parity B-2
physical cable length 2-9
,
2-10
port B-2
PPR 2-5
precision delay control 2-3
precompensation 2-5
priority B-2
pulse width 2-13
R
receiver B-2
latch 2-11
reconnect B-2
REQ/ACK input signals 2-15
request
(REQ) 2-13
reselect B-2
reset control
signals 2-12
RESET/ signal 3-5
retiming logic 2-2
S
S_CLK 3-6
S_DATA 3-6
SACK 2-13
SCSI
A side interface pins 3-3
B side interface pins 3-4
bidirectional
signals 4-4
bus distance requirements 1-4
,
2-8
bus mode changing 2-8
CRC 2-7
DIFFSENS signal 4-4
DT clocking 2-4
information unit transfers 2-6
ISI 2-4
paced transfers 2-4
packetized transfers 2-6
parallel interconnect 3 1-7