Avago Technologies LSI53C320 - Manual (Page 32)

2-14 Functional Descriptions
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
2.3.6 Control/Data, Input/Output, Message, and Attention Signals
The following steps describe the processing of these signals:
1. If the LSI53C320 is driving the signal, the LSI53C320 blocks the
input signal on the other bus.
2. The LSI53C320 filters the leading edge of the signal to ensure that
the output does not switch for a specified time after the leading edge.
The duration of the input signal determines the duration of the output
signal.
3. In the last stage, the LSI53C320 3-states the outputs.
4. To assure that the LSI53C320 does not sample its own signals, the
LSI53C320 delays sampling until a specified time after the last signal
deassertion.
2.4 Internal Control Descriptions
This section provides information about self-calibration, delay line
structures, and busy filters.
2.4.1 Self-Calibration
The LSI53C320 triggers self-calibration to adjust for variations in
temperature, process, and voltage every second during bus free states.
2.4.2 Delay Line Structures
The signal and control interfaces for bus to bus transfers require fixed
delay functions. The LSI53C320 uses programmable delay lines to
implement the delay functions. Multiplexers select the incremental points
in the delay chain. The LSI53C320 self-calibration manages the effects
of temperature and voltage changes.
2.4.2.1 Data Path
The data path through the LSI53C320 includes two levels of latches. The
first latch in the data path is located in the receiver and the REQ/ACK
input clock and generates a hold. This latch holds the received data to
capture incoming data that might have minimal setup and hold times. A