Avago Technologies LSI53C320 - Manual (Page 22)

2-4 Functional Descriptions
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
2.2.1.1 Double Transition (DT) Clocking
Ultra160 SCSI and Ultra320 SCSI implement DT clocking to provide
speeds up to 80 megatransfers per second (megatransfers/s) for
Ultra160 SCSI, and up to 160 megatransfers/s for Ultra320 SCSI. When
implementing DT clocking, a SCSI device samples data on both the
asserting and deasserting edge of REQ/ACK. DT clocking is only valid
using an LVD SCSI bus.
2.2.1.2 Intersymbol Interference (ISI) Compensation
ISI Compensation uses paced transfers and precompensation to enable
high data transfer rates. Ultra320 SCSI data transfers require the use of
ISI Compensation.
Paced Transfers – The initiator and target must establish a paced
transfer agreement that specifies the REQ/ACK offset and the transfer
period before using this feature. Devices can only perform paced
transfers during Ultra320 SCSI DT data phases. In paced transfers, the
device sourcing the data drives the REQ/ACK signal as a free running
clock. The transition of the REQ/ACK signal, either the assertion or the
negation, clocks data across the bus. For successful completion of a
paced transfer, the number of ACK transitions must equal the number of
REQ transitions, and both the REQ and ACK lines must be negated.
The P1 line indicates valid data in 4-byte quantities by using its phase.
The transmitting device indicates the start of valid data state by holding
the state of the P1 line for the first two data transfer periods. Beginning
on the third data transfer period, the transmitting device continues the
valid data state by toggling the state of the P1 line every two data
transfer periods for as long as the data is valid. The transmitting device
must toggle the P1 line coincident with the REQ/ACK assertion. This
method provides a minimum valid data period of two transfer periods.
To pause the data transfer, the transmitting device reverses the phase of
P1 by withholding the next transition of P1 at the start of the first two
invalid data transfer periods. Beginning with the third invalid data transfer
period, the transmitting device toggles the P1 line every two invalid data
transfer periods until it sends valid data. The transmitting device returns
to the valid data state by reversing the phase of the P1 line. The invalid
data state must experience at least one P1 transition before returning to