Avago Technologies LSI53C320 - Manual (Page 21)

Ultra320 SCSI Functional Description 2-3
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
A synchronous negotiation between devices forms a nexus, for which the
on-chip RAM stores information. This information remains in place until
a chip reset, power down, or renegotiation. The nexus information
enables the LSI53C320 to make accurate retiming adjustments.
2.1.3 Precision Delay Control Block
The Precision Delay Control block provides calibration information to the
precision delay elements in the Retiming Logic block. Since the
LSI53C320 voltage and temperature vary with time, the Precision Delay
Control block periodically updates the delay settings in the Retiming
Logic block to maintain constant and precise control over the bus timing.
2.1.4 State Machine Control Block
The State Machine Control block monitors the SCSI bus phases, the
initiator and target device IDs, and various timing functions. This block
controls the SCSI bus signal retiming and SCSI protocol implementation.
2.1.5 DIFFSENS Receiver Block
The LSI53C320 can operate with SE or LVD SCSI buses. The
DIFFSENS Receiver block determine the operating mode of the SCSI
bus by monitoring the voltage level on the DIFFSENS signal. For more
information, refer to
Section 2.2.2.1, “SCSI Bus Modes.”
2.2 Ultra320 SCSI Functional Description
The LSI53C320 supports Ultra320 SCSI. This interface expands the
bandwidth of the SCSI bus to allow faster synchronous data transfers of
up to 320 Mbytes/s. Ultra320 SCSI doubles the data transfer rate as
compared to the Ultra160 SCSI interface. This section describes how the
LSI53C320 implements the features in the SPI-4 draft specification.
2.2.1 Ultra320 SCSI Features
This section describes the Ultra320 SCSI features in the LSI53C320.