Avago Technologies LSI53C320 - Manual (Page 69)

Index IX-3
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
phases 2-3
precompensation 2-5
skew compensation 2-6
termination 2-8
TolerANT technology 1-7
Ultra320 B-2
features 2-4
SE 2-8
select (SSEL) 2-11
self-calibration 2-14
serial EEPROM 2-15
,
3-6
server clustering 1-3
signal
groupings 2-11
,
3-1
skew 2-2
signal drive strength 2-5
signals
busy control 2-12
reset control 2-12
select control 2-11
single-ended 1-1
skew compensation 1-5
,
2-6
slew rate 1-6
source bus 2-2
,
2-11
SP_CLK 2-15
SP_DAT 2-15
SREQ 2-13
state machine control 2-3
storage temperature 4-1
supply voltage 4-1
,
4-2
SureLINK 1-6
T
target B-2
termination B-2
test conditions
rise/fall time 4-7
thermal resistance 4-2
TolerANT 1-7
,
B-2
electrical characteristics 4-6
,
4-7
transceivers
LVDlink multimode 1-6
transfer active 3-5
transfers
information units 2-6
packetized 2-6
transmission mode
distance requirements 1-5
U
Ultra160 SCSI
DT clocking 2-4
Ultra320 SCSI 1-5
,
2-3
,
B-2
benefits 1-5
CRC 2-7
DT clocking 2-4
features 2-4
information unit 2-6
ISI 1-5
,
2-4
maximum cable length 2-8
paced transfers 2-4
packetized transfers 2-6
precompensation 2-5
skew compensation 1-5
,
2-6
V
VDD_CORE 3-6
VDD_SCSI 3-6
voltage 4-2
voltage levels
DIFFSENS 2-7
W
warm swap 3-5
WS_ENABLE/ 3-5
X
XFER_ACTIVE 3-5