Avago Technologies LSI53C320 - Manual (Page 50)

4-8 Specifications
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
Figure 4.4 Clock Timing
4.2 Chip Drawings
This section provides the BGA and mechanical drawings for the
LSI53C320.
4.2.1 Mechanical Drawing
Figure 4.5 illustrates the LSI53C320 mechanical drawing. The
LSI53C320 uses a 272-ball, PBGA package with a VG package code.
Table 4.12 Clock Timing
Symbol Parameter Min Max Units
t
1
Clock period 24.75 25.25 ns
t
2
Clock low time 10 15 ns
t
3
Clock high time 10 15 ns
t
4
Clock rise time 1 – V/ns
Clock
t
1
t
3
t
4
t
2