Avago Technologies LSI53C320 - Manual (Page 29)

SCSI Signal Processing 2-11
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
In designs that use a back plane, designers must additionally consider
the signal propagation velocity through the back plane to ensure that the
400 ns electrical cable length requirement is met.
2.3 SCSI Signal Processing
Figure 3.1 shows the LSI53C320 signal grouping. The following sections
describes the signal processing for the LSI53C320 SCSI signals. Refer
to
Section Chapter 3, “Signal Description,” and Section Chapter 4,
“Specifications,” for more information on individual signals.
2.3.1 Data and Data Parity Signals
The LSI53C320 passes the data and parity signals from the source bus
to the load bus and provides the necessary edge shifting to guarantee
the skew budget for the load bus. Either side of the LSI53C320 can act
as the source bus or the load bus. The side that the LSI53C320 receives
signals on is the source bus. The side that the LSI53C320 drives signals
on is the load bus. These steps describe the LSI53C320 data
processing:
1. The receiver logic accepts the data. Once the clock signal
(REQ/ACK) is received, the LSI53C320 gates the data from the
receiver latch.
2. The LSI53C320 holds the asserting edge for a specified time to
prevent signal bounce. The input signal controls the duration of the
hold time.
3. The LSI53C320 samples the bus using a latch, which provides a
stable data window for the load bus.
4. In the last stage, the LSI53C320 3-states the outputs.
5. To assure that the LSI53C320 does not sample its own signals, the
LSI53C320 delays sampling until a specified time after the last signal
deassertion.
2.3.2 Select Signal
A_SSEL and B_SSEL perform bus arbitration and selection. When a bus
asserts the SSEL signal, the LSI53C320 propagates the signal assertion