Avago Technologies LSI53C320 - Manual (Page 34)

2-16 Functional Descriptions
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
LSI Logic recommends using a 3.3 V, 2 Kbyte (256 x 8 bit) serial
EEPROM that can accept a 50 KHz clock.
Figure 2.5 provides a sample
layout.
Figure 2.5 Serial EEPROM Connection
10%
S_CLK
LSI53C320
CLK
DAT S_DATA
A2
A1
A0
WP
VCC
1.0
µ
F
4.75 K
Ω
10%
4.75 K
Ω
10%
4.75 K
Ω
10%
3.3 V
3.3 V 3.3 V
3.3 V
Serial EEPROM
(24C16)
C7
B6