Sundance SMT310Q - Manual (Page 4)

Version 2.1 Page 4 of 55 SMT310Q User Manual
8. Interrupts.......................................................................................................... 29
8.1 SMT310Q-To-PCI Interrupts ...................................................................... 29
8.2 PCI-To-SMT310Q Interrupts ...................................................................... 30
8.3 Interrupt Registers...................................................................................... 30
8.3.1 INTREG Register (BAR1, Offset 40
16
) ................................................ 31
9. Memory Maps .................................................................................................. 32
9.1 PCI Bus Memory Map ................................................................................ 32
9.1.1 PCI Bridge Chip Internal Register (BAR0) .......................................... 32
9.1.2 I/O Space Register Assignments (BAR1)............................................ 32
9.1.3 Memory Space Assignments (BAR2).................................................. 33
9.1.4 DMA Engine ........................................................................................ 33
9.2 Local Bus Memory Map.............................................................................. 34
10. Stand-Alone Mode ........................................................................................... 35
11. Specifications .................................................................................................. 36
11.1 Performance Figures.................................................................................. 36
11.2 Relative JTAG speed ................................................................................. 37
11.3 Mechanical Dimensions ............................................................................. 37
11.4 Power consumption.................................................................................... 37
12. Cables and Connectors .................................................................................. 38
12.1 SDB............................................................................................................ 38
12.1.1 SDB Connector ................................................................................... 38
12.2 Comports.................................................................................................... 38
12.2.1 FMS Cabling ....................................................................................... 38
12.2.2 Buffered Comport Cabling................................................................... 39
12.3 JTAG cabling.............................................................................................. 40
12.4 Reset and Config headers.......................................................................... 44
13. Expansion Header (J2).................................................................................... 45
14. JTAG Interface circuits ................................................................................... 46
14.1 Signal Description ...................................................................................... 46
15. Firmware Upgrades ......................................................................................... 48
15.1 CPLD and EPROM reprogramming ........................................................... 49
15.1.1 CPLDs updating .................................................................................. 49
15.1.2 EPROM updating ................................................................................ 51