Sundance SMT310Q - Manual (Page 26)

Version 2.1 Page 26 of 55 SMT310Q User Manual
7.4
DSP Signals
AE*/DE* active low address/data enable signals driven by the SMT310Q.
When the DSP has ownership of the bus, these signals are driven
low by the SMT310Q allowing the DSP to drive the address and
data pins.
CE0* the tri-state control for the DSP’s global bus control pins. This is
permanently tied low by the SMT310Q, as the control signals are
always enabled.
STRB1* the data strobe signal from the DSP’s global bus. It is driven low
when the DSP is carrying out an access cycle. The DSP waits for
RDY1* to be driven low by the SMT310Q to indicate transfer has
been completed. This transfer is carried out in synchronous burst
mode. The DSP pulls STAT0 low to signal when the burst transfer
has completed.
RDY1* an active low transfer acknowledgement, driven by the SMT310Q to
indicate that the current transfer has been completed.
STAT0
STAT1
STAT2
STAT3 the DSP Status line. When all of the signals are logic ‘1’ then the
DSP Global bus interface is in an idle state. When any of these
signals is driven low, the DSP is requesting ownership of the
SMT310Q’s local bus. STAT0 has a special meaning and is driven
low by the DSP to indicate the last data packet transfer.
A0–A30 the DSP’s global Bus address lines.
D0–D31 the DSP’s global Bus data lines
IIOF0
IIOF1
IIOF2 DSP Interrupt signals. These are open-collector signals on the
SMT310Q that can be driven by the DSP interrupt the host, or
driven by the host to interrupt the DSP