Memory maps, 1 pci bus memory map, 1 pci bridge chip internal register (bar0) – Sundance SMT310Q User Manual
Page 32: 2 i/o space register assignments (bar1), Pci bus memory map, Pci bridge chip internal register (bar0), I/o space register assignments (bar1)
Version 2.1
Page 32 of 55
SMT310Q User Manual
9. Memory Maps
All address information is given in bytes:
9.1
PCI Bus Memory Map
9.1.1 PCI Bridge Chip Internal Register (BAR0)
Please see the User Manual for the V363EPC Local Bus PCI Bridge chip,
, for
details of internal registers.
9.1.2 I/O Space Register Assignments (BAR1)
In target mode, a host device accesses the SMT310Q across the PCI bus,
which gives access to the target mode registers. The operating system or
BIOS will normally allocate a base address for the target mode registers of
each SMT310Q. Access to each register within the SMT310Q is then made at
offsets from this base address as shown in the table below.
Offset
Register (Write)
Register (Read)
Width
00
16
- -
04
16
- -
08
16
- -
0C
16
- -
10
16
COMPORT_OUT COMPORT_IN
32
14
16
CONTROL STATUS
32
18
16
INT_CONTROL
32
1C
16
- -
20
16
to 3F
16
COMPORT Configuration
COMPORT
Configuration
24
16
COM_SWITCH COM_SWITCH
16
40
16
INTREG
INTREG
16
80
16
to AF
16
TBC Write
TBC Read
16
Table 8: I/O address space map