Sundance SMT310Q - Manual (Page 10)

Version 2.1 Page 10 of 55 SMT310Q User Manual
3.2
V363EPC PCI Bridge Chip
The PCI Bridge connects the host PCI bus to various devices on the local bus:
• Quick Logic EPC363 bridge chip. This has a 32-bit, 33MHz PCI
interface that supports I 2 C control, mailbox register access, and direct
memory reads and writes;
• Input and output FIFO. This is capable of transferring 256 32-bit words
of data to and from the DSP at 33MHz, bursting at a maximum local bus
transfer rate of 132MB/s;
• Address apertures. These provide access to the V363EPC bridge chip
configuration registers or bridging functions. The apertures respond to
addresses on both the PCI and Local buses. The following apertures are
available on the SMT310Q:
o
Four data transfer apertures to transfer data across the bridge.
Two apertures are for PCI to local transfers (BAR1 and BAR2)
and two are for local to PCI transfers (Local-to-PCI Aperture 0 and
Local-to-PCI Aperture 1).
o
Two apertures to access the bridge chip’s internal registers: one
aperture for Local Bus (PCI Bridge Register) accesses and one for
PCI bus (BAR0) accesses.
3.3
JTAG controller
The JTAG controller is based on the TI 8990 device; Code Composer Studio
drivers are available from Sundance, Part Number
SMT6012 . The presence of
a TIM in a module site causes its SENSE pin to switch the module into the
JTAG chain.
3.4
Shared SRAM
The Master TIM can access the SRAM over the Local Bus at transfer rates up
to 100MB/s. The number of wait-states required by the Master TIM varies
depending on the speed of the module. Maximum access rates use a 20ns
strobe cycle.
3.5
Control EPLD
The EPLD acts as an on-board arbitration unit that controls which device has
access to the Local Bus resources.