Sundance SMT310Q - Manual (Page 24)

Version 2.1 Page 24 of 55 SMT310Q User Manual
The mailbox registers are on byte boundaries with offsets C0
16
–CF
16
, from
LB_IO_BASE. As all DSP global bus accesses are carried out in aligned 4-byte
units, a write access over the global bus to 1C000000
16
+ C0
16
will write to the
first 4 mailbox registers in the PCI bridge device.
The mailbox registers are accessed from the PCI bus through the PCI-to-
Internal Register (PCI_IO_BASE) aperture. This is accessed via the PCI Bridge
Chip Internal Register (BAR0, byte offset C0
16
–CF
16
).
7.1.1 Doorbell Interrupts
Each of the 16 mailbox registers can generate four different interrupt requests
called doorbell interrupts. Each of these requests can be independently
masked for each mailbox register. The four doorbell interrupt types are:
• DSP interrupt request on read from PCI side
• DSP interrupt request on write from PCI side
• PCI interrupt request on read from DSP side
• PCI interrupt request on write from DSP side
The PCI read and DSP read interrupts are ORed together and latched in the
mailbox read interrupt status register (MAIL_RD_STAT). Similarly, the PCI
write and DSP write interrupts are ORed together and latched in the mailbox
write interrupt status register (MAIL_WR_STAT). All of the interrupt request
outputs from the status registers are ORed together to form a single mailbox
unit interrupt request and routed to both the Local and PCI Interrupt Control
Units.
When several mailbox registers are accessed simultaneously, for example
when 4 mailbox registers are read as a word quantity, then each register
affected will request a separate interrupt if programmed to do so.
See section 8. for further information on Interrupts.
7.2
DSP Interrupt Control
Interrupts can be enabled from a number of different sources i.e. DSP►Host
and Host►DSP. See section 8. for a description of these functions.