Sundance SMT310Q - Manual (Page 30)

Version 2.1 Page 30 of 55 SMT310Q User Manual
8.2
PCI-To-SMT310Q Interrupts
TIMIIOF0
TIMIIOF1
TIMIIOF2
CONTROL
REGISTER
CONTROL CPLD
LINT LINT
LINT can
be caused
by any PCI
interrupt
e.g. Mailbox
IIOF0
IIOF1
IIOF2
PCI
Bridge
INTREG
REGISTER
TIMIIOF0 IE
TIMIIOF1 IE
TIMIIOF2 IE
Figure 10: PCI to SMT310Q Interrupts
8.3
Interrupt Registers
The following registers are used to control PCI►DSP and DSP►PCI interrupts:
• PCI bridge internal register
• PCI Interrupt Configuration (BAR 0, 4C
16
)
• PCI Interrupt Status (BAR 0, 48
16
)
• Local Bus Interrupt Mask (BAR 0, 77
16
)
• Local Bus Interrupt Status (BAR 0, 76
16
)
• PCI Mailbox Write Interrupt Control (BAR 0, D0
16
)
• PCI Mailbox Read Interrupt Control (BAR 0, D2
16
)
• Local Bus Mailbox Write Interrupt Control (BAR 0, D4
16
)
• Local Bus Mailbox Read Interrupt Control (BAR 0, D6
16
)
• Mailbox Write Interrupt Status (BAR 0, D8
16
)
• Mailbox Read Interrupt Status (BAR 0, DA
16
)