Sundance SMT310Q - Manual (Page 19)

Version 2.1 Page 19 of 55 SMT310Q User Manual
4.3.4 Interrupt Control Register (BAR1, Offset 18
16
)
This write-only register controls the generation of interrupts on the PCI bus.
Each interrupt source has an associated enable and clear flag. This register can
be written with the contents of bits 7:0 of the Status Register. The JTAG
controller generates TBC INT and must be cleared of all interrupt sources in
order to clear the interrupt.
10 9
DSP-PC IIOF2 En DSP-PC IIOF1 En
8 7 6 5 4 3 2 1 0
DSP-PC
IIOF0 En
CLEAR
C40 INT
0 CLEAR
IBF INT
CLEAR OBE
INT
C40 IE TBC IE IBF IE OBE IE
DSP-PC IIOF2 En Enables DSP-PC interrupts on IIOF2
DSP-PC IIOF1 En Enables DSP-PC interrupts on IIOF1
DSP-PC IIOF0 En Enables DSP-PC interrupts on IIOF0
IBF IE Comport Input Buffer Full Interrupt Enable. Allows an interrupt to be generated
when the host comport input register is loaded with data from the C40.
OBE IE Comport Output Buffer Empty Interrupt. Allows an interrupt to be generated
when the host comport register has transmitted its contents.
TBC IE Test Bus Controller Interrupt Enable. Interrupts from the Texas JTAG controller
are enabled when set.
C40 IE C40 Interrupt Enable. Allows a programmed interrupt to be generated by the
C40 when set.
CLEAR OBE INT Write a one to this bit to clear the interrupt resulting from a comport output
event.
CLEAR IBF INT Write a one to this bit to clear the interrupt event resulting from comport input.
CLEAR C40 INT Write a one to this bit to clear down the C40 INT event.
Table 5: Interrupt Control Register
4.4
Comport Direction
Comports will automatically switch direction during the execution of a program,
but when they come out of reset, they will be set to an initial direction: input or
output. You should always ensure that you only ever connect pairs of comports
that reset to opposite initial directions.
Comports resetting as inputs 3, 4, 5
Comports resetting as outputs 0, 1, 2