Measurement Computing ADAC/5500 Series - Manual (Page 49)

Zero Drift: ±2 ppm/ °C
Signal to Noise and Distortion: S/(N+D) 73 dB min. @ gain = 1
Total Harmonic Distortion: -90dB (typical) @ gain = 1, measured to 5th harmonic
Full Power Bandwidth: 250 kHz
Input Impedance
Shunt Res. to Ground: 10 M ohm
Shunt Capacitance: 28 pf
On Resistance: 400 ohm
Over-voltage Protection: ±25 V (powered)
±40 V (unpowered)
Acceptable Operating Limit
Signal Plus Common Mode: ±12 V
Output Coding
Unipolar: Straight binary
Bipolar: Offset binary 2's complement
Gain/Channel/Sequence Selection: 256 element RAM
Data Format: 16-bit right justified
6.2.2 A/D Trigger – ADAC/5501MF and ADAC/5502MF
Clock Sources: - software
- on board programmable pacer
- user defined external TTL
External Clock Input Delay: - 100ns uncertainty
Trigger Sources: - software
- on board (burst mode)
- external (TTL)
Triggering Modes: - software gate
- external gate
- periodic burst
- pre-trigger (sample until trigger)
- post-trigger (sample after trigger)
- about-trigger (sample before and after trigger)
External Trigger Input Delay: - 100ns uncertainty
ADAC Series 908196
-44- ADAC/5500 Series User’s Manual