Measurement Computing ADAC/5500 Series - Manual (Page 25)

ADAC Series PCI Boards 795 - 20 - ADAC/5500 Series User Manual
The ADCLKOUT signal line is shared with the on-board TIMER 1 Clock Output
signal (TMR1) pin #5 on the 68-pin J1 connector. Therefore only one output signal
may be generated to the ADCLKOUT / TMR1 terminal at any given time. The
TIMER 1 is automatically disabled in hardware when the ADCLKOUT is enabled.
ADTGIN - This is the External ADC Trigger/Gate input. This input recognizes TTL level signals
and is used to start or stop the ADC acquisition process. The input is selectable as either rising/falling
edge or active high/low level sensitivity.
ADTGOUT - This signal is the internal ADC’s Trigger output. Each time the ADC is triggered from
any of the available triggering sources the ADTGOUT signal pulses high for a period of 1
microsecond. This output can be used to synchronize multiple A/D converters on different
ADAC/5500 cards allowing simultaneous A/D triggering by connecting the ADTGOUT to the
ADTGIN input of each PCI card.
The ADTGOUT signal line is shared with the on-board TIMER 0 Clock Output
signal (TMR0) pin #4 on the 68-pin J1 connector. Therefore only one output signal
may be generated to the ADTGOUT / TMR0 terminal at any given time. The
TIMER 0 is automatically disabled in hardware when the ADTGOUT is enabled.
DACLKIN - This is the External DAC0 Pacer clock input. This input recognizes TTL level signals
and is edge sensitive. The active edge is selectable as either rising or falling.
The DACLKIN signal line is shared with the on-board COUNTER 1 Clock Input
signal (CNTR1) pin #40 on the 68-pin J1 connector. Therefore only one input signal
may be connected to the DACLKIN / CNTR1 terminal at any given time. Attemp-
ting to use COUNTER 1 when the DAC Pacer Clock Source is set for an External
Clock Input would not be possible unless COUNTER 1 was being used to count the
DAC’s External Clock Input signal.
DATGIN - This is the External DAC0 Trigger/Gate input. This input recognizes TTL level signals
and is used to start or stop the DAC acquisition process. The input is selectable as either rising/falling
active edge or active high/low level sensitivity.
4.2.1.5 Counters And Timers
CNTR0 - This is the general purpose Counter 0 clock input. This input recognizes TTL level signals
and is rising edge sensitive. The input clock rate cannot exceed 500 kHz. The clock source must
provide a minimum pulse width of 100 ns.
The COUNTER 0’s External Clock Input line (CNTR0) is shared with the ADC’s
External Clock Input signal (ADCLKIN) pin #39 on the 68-pin J1 connector.
Therefore only one input signal may be connected to the ADCLKIN / CNTR0
terminal at any given time. Attempting to use COUNTER 0 when the ADC Pacer
Clock Source is set for an External Clock Input would not be possible, unless
COUNTER 0 was being used to count the ADC’s External Clock Input signal.
928