Measurement Computing ADAC/5500 Series - Manual (Page 41)

ADAC Series PCI Boards 795 - 36 - ADAC/5500 Series User Manual 928
5.2.7 Clocking the DAC
Two DAC channels are provided. The clock source of the primary DAC0 channel may be any of the following:
1) Software Command
2) DAC0 Pacer Clock
3) External Event (DACLKIN).
The clock source for the secondary DAC1 channel is limited to the following sources:
1) Software Command
2) DAC1 Pacer Clock
3) Channel 0 Clock Source.
The DAC processes, once started, immediately copy the next data sample to a holding register. Upon receipt of a DAC
clock, the analog output immediately changes to the current value in the holding register, and the next data sample is
immediately copied from system memory into the holding register. If the DACs are clocked before their previous
outputs have fully settled, their outputs will simply begin slewing to the new level.
5.2.7.1 DAC Software Generated Single Clock
A single D/A conversion may be initiated by a software generated clock. The DAC will output the next FIFO
data sample for the selected DAC channel. After issuing the software convert command, the DAC READY
flag is monitored to determine when the conversion has completed, and DAC is ready for the next conversion.
5.2.7.2 DAC Pacer Clocking
A series of DAC conversions may be controlled by the on-board pacer clock. This timer may be programmed
to generate a periodic clock rate as high as 200 kHz or as slow as 4 samples per hour. Refer to section 5.2.8
Starting (Triggering) a DAC Acquisition for information on triggering (starting) a clocked acquisition.
5.2.7.3 DAC External Event Clocking
Conversions may also be caused by an external event. DACLKIN is an edge sensitive input that can be
programmed to cause conversions. The DACLKIN is selectable as either rising or falling edge sensitive.
5.2.7.4 DAC Maximum Clock Rate
The maximum rate which the DAC should be clocked and retain optimal accuracy is limited by the DAC chip
itself. These limits may not be exceeded. If the pacer clock is run faster, some of the clock pulses will be
ignored by the circuitry, and the clock error flag will set.
5.2.8 Starting (Triggering) a DAC Acquisition
There are several methods that can be used to initiate an acquisition. All of these are achieved by triggering or gating
the DAC clocks mentioned previously in section 5.2.7 Clocking the DAC. Note that a trigger is an edge active event
and gate is a level controlled enable. Note also that all trigger and clocking functionality is available for the primary
DAC channel 0. The secondary DAC channel 1 is limited to software control methods (no external trigger or clock)
except that it can be synchronized to output samples simultaneously with channel 0. In this latter mode, it performs
identically to channel 0 as far as triggering and clocking methods are concerned.
1) Software Gate
2) External Gate (DATGIN)
3) External Trigger (DATGIN)
5.2.8.1 DAC Software Gate
The software Control Gate Enable (CGEN) may be used to allow the starting and stopping of the on-board
DAC pacer clock. CGEN may not be used to control the external clock input (DACLKIN).