Measurement Computing ADAC/5500 Series - Manual (Page 15)

ADAC Series PCI Boards 795 - 10 - ADAC/5500 Series User Manual 928
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The ADAC/5500MF analog inputs are impedance buffered. They can only be referenced in Single-
Ended input configuration. A 176 element channel-configuration RAM is provided to allow each ADC
channel to be programmed with a different Range. Note that input range selection also applies to
expansion channels located on the ADAC line of accessory screw terminal boards. The termination
boards are detailed in section 4.3.
The analog inputs on the ADAC/5500, ADAC/5501MF, ADAC/5502MF, ADAC/5503HR and
ADAC/5504HR may be configured for either
±10 V bipolar or 0-10 V unipolar operation. The input
range is programmable on a channel-by-channel basis in a 176-element channel configuration RAM. Note
that the range selection also applies to expansion channels.
The programmable gain circuitry on the ADAC/5501MF, ADAC/5502MF, ADAC/5503HR and
ADAC/5504HR must be taken into account in defining the usable error free input range. The boards
provide a wide range of programmable ranges and resolutions.
The ADAC/5500 Series Boards each bring out ±15 V and +5 V to the main I/O connector (J1). In
addition, the ADAC/5501MF, ADAC/5502MF, ADAC/5503HR and ADAC/5504HR bring +5 V to the
auxiliary digital I/O connectors (P3 and P5), located on the backside of those boards. These power lines
are individually fused to protect the ADAC/5500 Series Board. Note that connecting or disconnecting
cables or screw terminal panels (as well as any user connections to these power lines) may blow a fuse, or
cause damage to the board.
Incorrect connection of user wiring is one of the most common problems experienced by users of data
acquisition boards. To ensure proper results, you must first determine what type of signal source you are
measuring (Ground Referenced Source or Floating Source), and then choose the appropriate input
configuration on your data acquisition card (Differential, Pseudo-Differential, or Single-Ended). Chapter
4 of this manual includes detailed information.
3. HARDWARE CONFIGURATION
The ADAC/5500 Series contains no hardware jumpers; all board configuration elements are software selectable. Data-
acquisition settings such as analog input, data collection rates, input voltage range, and operating modes are configured
through application software. ADAC ADLIB WDM software drivers provide an application level software interface to
Windows 98/ME/NT/2000/XP. Software packages such as LabVIEW
™ communicate through our ADLIB driver
software. These packages configure and collect, or output, acquisition data in a GUI based interface.
3.1 DMA AND INTERRUPT UTILIZATION
The PCI specification uses a shared interrupt scheme to increase the availability of interrupts in an attempt to alleviate
limitations imposed by ISA interrupt constraints. This shared interrupt scheme, known as interrupt chaining, comes at a
price. When a PCI card that uses interrupts is installed into a PC, the system software adds the device to a list of
interrupt service routines for all PCI devices that share a common interrupt signal. When a PCI device generates an
interrupt, the system software detects the interrupt and executes the first Interrupt Service Routine (ISR) in the list. The
first routine in the list may not be your data acquisition device. If not, the first device determines if its device asserted
the interrupt, if so the software services the interrupt and returns. The processor immediately interrupts again because
the second device is still generating an interrupt request. The processor again jumps to the first device in the list, the
device determines it has not requested an interrupt and jumps to the entry point of the second ISR to be serviced. If the
first device in the list were to generate interrupts at a high frequency, the second device might over-run or under-run,
generating an error condition while awaiting service. Well-behaved PCI devices generate interrupts infrequently.
ADAC driver software only determines if the ADAC board has requested an interrupt, if so it defers the ISR to a
callback procedure and quickly returns control to the interrupted process. Now that the facts are on the table, interrupt
latency on the PCI bus can be extremely inefficient for high-speed data acquisition. To overcome this inefficiency we
incorporate an on-board DMA engine analogous to the older ISA type of DMA controller. The on-board DMA engine