Measurement Computing ADAC/5500 Series - Manual (Page 36)

ADAC Series PCI Boards 795 - 31 - ADAC/5500 Series User Manual 928
ADC Acquisition
This term is used to refer to a series of A/D conversions. This series may consist of sampling a single channel several
times or sampling several channels sequentially one or more times. An acquisition has a clearly defined Starting point
and Ending point. Thus an acquisition may be STARTED and STOPPED.
DAC Acquisition
This term is used to refer to a series of D/A conversions. This series may consist of outputting a single DAC channel
several times or outputting both channels simultaneously one or more times. An acquisition has a clearly defined
Starting point and Ending point. Thus an acquisition may be STARTED and STOPPED.
ADC and DAC Clock
This is the signal or impetus that initiates an A/D or D/A conversion. To CLOCK the ADC or DAC is to start an A/D
conversion. The term clock is used for this process because typically a clock signal consists of a series of pulses that are
periodic or evenly timed. If the conversions are evenly spaced it is then possible to digitally reconstruct the input
waveform without distorting its component frequencies.
ADC and DAC PACER Clock
This is a timed periodic signal that may either directly clock the ADC/DAC or initiate a burst of ADC conversions.
Thus the PACER clock is exclusive to both the ADC and DAC channels.
ADC BURST Clock
This is also a timed periodic signal that may be used to directly clock the ADC. When the Burst clock is used, this
signal defines the time between individual conversions. This signal is not, however, continuous. It lasts for a predefined
number of pulses and then stops. The duration of this signal is called the burst clock; and the period of individual pulses
is the burst rate. The ADC Pacer Clock initiates Bursts.
ADC and DAC Trigger
This is the signal or impetus that initiates or terminates an Acquisition. Essentially the Trigger Starts or Stops the ADC
or DAC PACER Clock.
ADC Channel Configuration RAM
This is the term used for the ADC’s Channel, Gain, Range, and Input Configuration lookup table. The length of this
table can be anywhere from 1 element to 176 elements. When an ACQUISITION is in process, the board will
sequentially go through this list to determine the channel and gain setting for the next conversion. Thus, channels may
be sampled in any order and at any gain. Note, however, that for maximum performance, it is recommended that
channels with like gains be grouped together in the sample sequence.
ADC Polled
This is an acquisition mode in which all aspects of the data collection is handled directly. Specifically, once an A/D
conversion is initiated, the software must POLL the ADC’s status register testing for a DATA available flag to set and
data is then read from the board. This mode requires the most software overhead.
DAC Polled
This is an acquisition mode in which all aspects of the data collection is handled directly. Specifically, once a D/A
conversion is initiated, the software must POLL the DAC’s status register testing for a DATA ready flag to set before
the next DAC conversion can be initiated. This mode requires the most software overhead.