Measurement Computing ADAC/5500 Series - Manual (Page 24)

ADAC Series PCI Boards 795 - 19 - ADAC/5500 Series User Manual
4.2.1.1 Analog Input Channels
These channel signals are over-voltage protected to 20 V above or below the ±15 V power supply. The
channel inputs can withstand input voltages of up to ±20 volts when the power to the system is off.
ADAC-TB-8
CH 0..CH 7 - These signals are the positive half of the associated single-ended input channels.
ADAC-TB-16
CH 0..CH 14 EVEN - These signals are either the positive half of the associated differential input
channel pairs 0 through 7, or single-ended/pseudo-differential input channels 0 through 14 even.
CH 1..CH 15 ODD - These signals are either the negative half of the associated differential input
channel pairs 0 through 7, or single-ended/pseudo-differential input channels 1 through 15 odd.
4.2.1.2 Analog Outputs
DAC 1, DAC 0 - These signals are the voltage output signals from the optional DACs.
RTN 1, RTN 0 - These signals are the return lines for the voltage outputs. These inputs are
essentially tied to AGND (Analog Ground) on the board.
4.2.1.3 Digital I/O Lines
DIO 0..DIO 15 - These signals are the 16 TTL level digital controls lines configurable as 8 bit input
or output lines. These lines are not clocked.
4.2.1.4 Terminal Panel Control
These signals are used to control the various optional terminal panels. The function of some signals may vary
slightly depending on the panel used.
MUX 0..MUX 7 - These signals are used to control the external multiplexers on active panels. These
lines directly reflect the current state of the Channel RAM bits of the same name.
ADCLKIN - This is the ADC External Pacer clock input. This input recognizes TTL level signals
and is edge sensitive. The active edge is selectable as either rising or falling.
The ADCLKIN signal line is shared with the on-board COUNTER 0 Clock Input
signal (CNTR0) pin #39 on the 68-pin J1 connector. Therefore only one input signal
may be connected to the ADCLKIN / CNTR0 terminal at any given time. Attemp-
ting to use COUNTER 0 when the ADC Pacer Clock Source is set for an External
Clock Input would not be possible, unless COUNTER 0 was being used to count the
ADC’s External Clock Input signal.
ADCLKOUT - This signal is the ADC’s External Clock Output. Each time the ADC is clocked from
any of the available clocking sources the ADCLKOUT signal pulses high for a period of 1
microsecond. This output can be used to synchronize multiple A/D converters on different PCI cards
allowing simultaneous A/D conversions by connecting the ADCLKOUT to the ADCLKIN input of
each PCI card.
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