Measurement Computing ADAC/5500 Series - Manual (Page 42)

ADAC Series PCI Boards 795 - 37 - ADAC/5500 Series User Manual 928
5.2.8.2 DAC External Gate
The DAC0 clock may be “switched On” (and Off) with the external DATGIN input. The input is level
sensitive and selectable as either active high or active low control. If the on-board pacer clock drives the
DAC0 the external gate input is used to enable and disable the DAC0’s pacer clock after being polarity
conditioned. The DAC0 clock will be enabled as long as the external gate input is in the active state.
5.2.8.3 DAC External Trigger
The external gate/trig input (DATGIN) may also be configured as a rising or falling edge sensitive input to
trigger the start of the DAC0 clock. External triggers are ignored until the DAC0 is enabled. Once the DAC0
is enabled, the next active edge signal on DATGIN will enable the DAC0 Clock source. To disable the clock,
refer to section 5.2.9, Stopping a DAC Acquisition (CLOCK).
5.2.9 Stopping a DAC Acquisition (CLOCK)
The current acquisition will halt under several circumstances. The most basic method is to simply disable the DAC by
setting the Conversion Enable bit, CVEN, to 0. This will effectively shut off the DAC and re-prime the trigger inputs.
Other methods to stop the acquisition are:
1) Software Gate
2) External Gate (DATGIN)
5.2.9.1 DAC Software Gate
To stop the DAC clock when operating in software gated mode, simply disable the Control Gate Enable
(CGEN). Refer to section 5.2.3.1 ADC Software Gate for additional information on this mode.
5.2.9.2 DAC External Gate
The DAC0 clock may also be “switched off” with the external trig/gate input (DATGIN). Refer to section
5.2.3.2 ADC External Gate for additional information about this mode.
5.2.9.3 DAC Clock and FIFO Errors
When the DACs are running using DMA operating modes, the board will automatically interrupt if the Clock
Error Flag (CERR), FIFO Empty Flag (FE) or FIFO Error Flag (FERR) becomes active (i.e. set). These
interrupt sources are automatically enabled when using DMA.
5.2.10 DAC Data Transfer Mode
DAC data can be written directly to the on-board DA_FIFO 3 register or read directly from system memory to the
DA_FIFO via the on-board DMA engine. Each DA_FIFO data register implements a 32-bit read access from the PCI
bus. Two data samples are transferred during each DMA access. The first data sample always occupies the upper bits
(31-16) while the second sample always occupies the lower bits (15-0). Either DAC channel may be enabled or
disabled from their DA_CTRL registers. If either of the DAC channels is disabled, data is only sent to the enabled
channel(s). Both DAC channels can be independently configured in either POLLING or DMA modes. For POLLING
mode, each write to the DA_FIFO will immediately be output to, and update, the selected DAC channel(s). For DMA
mode, the on-board DMA engine directly reads data points from system memory to the DA FIFO register, thus
providing the fastest means of outputting DAC Data. Two 32-bit DMA memory pointer registers and two 16-bit
memory sample count registers provide for continuous DMA transfers. All PCI bus transfers are 32-bit operations. By
transferring two analog data points from system memory simultaneously to the destination DAC FIFO in one PCI bus
operation, the ADAC PCI cards are twice as efficient as 16-bit PCI implementations. Furthermore, skew between the
DAC0 and DAC1 channel can be entirely eliminated by using the linked clocking mode.
5.2.10.1 Software Polled DAC Acquisition Mode
This mode is the most CPU intensive acquisition mode. Basically the READY flag is monitored until the DAC
indicates it is ready to accept new data and then the DAC output is updated by writing the next data sample to
the DAC FIFO.
3 In this discussion, DA_FIFO refers to either DA0_FIFO or DA1_FIFO.