Measurement Computing ADAC/5500 Series - Manual (Page 38)

ADAC Series PCI Boards 795 - 33 - ADAC/5500 Series User Manual 928
The second factor involves the front-end circuitry. The bandwidth of the front-end will vary depending on the
gain setting (and the required resolution). The bandwidth will limit the maximum signal frequency the board
can pass. Essentially, when sampling a single channel repeatedly, the ADC may be operated up to its
maximum speed, but the front-end will filter out any frequency components of the input signal that exceeds
the bandwidth of the system.
When changing channels, even if the input signal is static, the front-end is required to respond to a changing
input each time the channel is changed. The net effect is that the maximum sampling speed of the ADC is
limited to the bandwidth of the front-end when changing channels.
Each time a conversion is initiated, the ADC goes into hold mode and the front-end begins to settle on the next
channel. At this point a timer is started. The duration of the timer is determined by the gain setting. If a new
conversion is begun before the timer completes its cycle, the clock error flag, CERR, will set indicating the
front-end has not settled sufficiently and the accuracy of the data may be compromised. The timer cannot,
however, determine whether the channel has actually changed or not. For example, if the front-end bandwidth
is 33 kHz but only a single channel is sampled at 100 kHz, the CERR flag will set even though the data is
accurate.
The following table indicates the bandwidth and sampling rates for each of the models at different gains, and
at what sample rate the error flag will set. Use this table as a guide in determining sampling rates and correct
error flag interpretation.
Product Gain
Front End
Bandwidth
(minimum) Max Sample
Rate*
Error Flag sets
if rate above
12-bit ADC ×1, ×2, ×4, ×8 166 kHz 100 kHz 100 kHz
×1, ×10 166 kHz 100 kHz 100 kHz
×100, ×1000 16 kHz 33 kHz 33 kHz
16-bit ADC ×1, ×2 50 kHz 200 kHz 200 kHz
×4, ×8 25 kHz 50 kHz 50 kHz
×1 50 kHz 100 kHz 100 kHz
×10 25 kHz 50 kHz 100 kHz
×100 5 kHz 10 kHz 1 kHz
* NOTE: Max Sample Rate applies only if input channel is changing. For single channel acquisition, the
max sample rate equals the max rate of the ADC itself (100 kHz or 200 kHz) regardless of gain.
5.2.3 Starting (Triggering) an ADC Acquisition
There are several methods that can be used to initiate an acquisition, all of these are achieved by triggering or gating the
ADC clock as mentioned previously. Note that a trigger is an edge active event and a gate is a level controlled enable.
An acquisition can be initiated via the following:
1) Software Gate
2) External Gate (ADTGIN)
3) External Trigger (ADTGIN)
5.2.3.1 ADC Software Gate
The software Control Gate Enable bit (CGEN
2
) may be used to allow the starting and stopping of the on-board
ADC pacer clock. CGEN may not be used to control the external clock input (ADCLKIN).
2 Control bits are grouped together in the AD_CTRL register.