Measurement Computing ADAC/5500 Series - Manual (Page 39)

ADAC Series PCI Boards 795 - 34 - ADAC/5500 Series User Manual 928
5.2.3.2 ADC External Gate
An ADC clock may be “switched On” (and Off) with the external ADTGIN input. The input is level sensitive
and selectable as either active high or active low control. If the on-board pacer clock drives the ADC, the
external gate input is used to enable and disable the ADC’s pacer clock after being polarity conditioned. The
ADC clock will be enabled as long as the gate input is in the active state.
5.2.3.3 ADC External Trigger
The external gate/trig input (ADTGIN) may also be configured as a rising or falling edge sensitive input to
trigger the start of the ADC clock. External triggers are ignored until the ADC is enabled. Once the ADC is
enabled, the next active edge signal on ADTGIN will enable the ADC Clock source. To disable the clock,
refer to Section 5.2.4 Stopping an ADC Acquisition (CLOCK).
5.2.4 Stopping an ADC Acquisition (CLOCK)
The current acquisition will halt under several circumstances. The most basic method is to simply disable the ADC by
setting the Conversion Enable control bit, CVEN, to 0. This will effectively shut-off the ADC and re-prime the trigger
inputs.
An acquisition can be halted via the following:
1. Software Gate
2. External Gate (ADTGIN)
3. External Trigger (ADTGIN)
5.2.4.1 ADC Software Gate
To stop the ADC clock when operating in software gated mode, simply disable the Control Gate Enable
(CGEN). Refer to Section 5.2.3.1 ADC Software Gate for additional information on this mode.
5.2.4.2 ADC External Gate
An ADC clock may also be “switched off” with the external trig/gate input (ADTGIN). Refer to Section
5.2.3.2 ADC External Gate for additional information about this mode.
5.2.4.3 ADC External Trigger
The external gate/trig input (ADTGIN) may also be used to stop an acquisition. In this mode, referred to as
ABOUT Trigger Mode, the ADC is disabled after a certain number of conversions are performed following a
trigger. The number of conversions may be anywhere from 1 to 65,536, which represents the number of post
trigger conversions. Once triggered, the ADC Conversion Counter immediately increments following each
conversion until it reaches 0, whereupon ADC conversions are automatically disabled. If the timer is loaded
with a value of -1, the ADC will be stopped after one valid clock. If this register is loaded with the value 0, the
full count (65,536 conversions) will occur.
Note that the Software and External Gate modes described in Section 5.2.3 Starting (Triggering) an ADC
Acquisition are ignored, i.e., the trigger source is always external when in the ABOUT Trigger Mode.
If the External Trigger input is disabled, conversions are enabled as soon as the ADC is enabled and the next
valid trigger will enable the internal counter to count conversions. If the External Trigger input is enabled, the
first external trigger will start the conversions and the next valid trigger will enable the internal counter to
count conversions.