Measurement Computing ADAC/5500 Series - Manual (Page 37)

ADAC Series PCI Boards 795 - 32 - ADAC/5500 Series User Manual 928
ADC and DAC DMA
Short for Direct Memory Access, DMA is the most self-sufficient of the Acquisition Modes available over the PCI bus.
In this mode, data from each conversion is automatically transferred directly from the ADAC/5500 board to or from
some pre-specified block of system memory. Essentially, DMA allows the acquisition process to run in the background
with virtually no software overhead.
5.2.2 Clocking the ADC
The source of the ADC clock may be any of the following:
1) Software Command
2) Pacer Clock
3) External Event (ADCLKIN)
4) Burst Clock
Once an ADC clock is received, the Analog input is immediately sampled. Converted data will become available
within 10 microseconds of the clock (max) for 12-bit boards, and 5 microseconds (max) for 16-bit boards. Any attempt
to clock the ADC while an A/D conversion is currently running will result in a Clock Error.
5.2.2.1 ADC Software Generated Single Clock
A single A/D conversion may be initiated by a software generated clock. The ADC will sample the voltage
present on the channel selected by the Channel configuration RAM. After issuing the software convert
command, the FNE
1 flag in the AD_STATUS register is monitored to determine when the conversion has
completed, and data is available to be read out of the AD_FIFO register.
5.2.2.2 ADC Pacer Clocking
A series of A/D conversions may be controlled by the on-board pacer clock. This timer can be programmed to
generate a periodic clock rate up to the ADC’s maximum rate or as slow as 4 samples per hour.
5.2.2.3 ADC External Event Clocking
Conversions may also be caused by an external event. ADCLKIN is an edge sensitive input that can be
programmed to cause conversions. The ADCLKIN is selectable as either rising or falling edge sensitive.
5.2.2.4 ADC Burst Clocking
This mode uses the Burst Rate clock to initiate conversions. The Burst Rate is defined as the time between
ADC conversions and the duration of the burst is defined Burst Length. When burst mode is enabled, each
burst will be started by any of the three previously mentioned clock sources.
5.2.2.5 ADC Maximum Clock Rate
The maximum rate which the ADC should be clocked and retain optimal accuracy will vary depending on
several factors. These include ADC resolution (12 or 16-bits), gain setting, and sampling mode.
The first limiting factor is the ADC chip itself. Boards with 12-bit ADC chips are capable of performing
analog to digital conversions at up to 100 kilo-samples per second. Models with 16-bit ADC chips will sample
at rates up to 200 kilo-samples per second. These limits may not be exceeded. If the sample clock is run faster,
some of the clock pulses will be ignored by the circuitry, and a clock error will be generated.
1 FIFO and DMA control bits and ADC status flags are grouped together in the AD_STATUS register.