Measurement Computing ADAC/5500 Series - Manual (Page 43)

ADAC Series PCI Boards 795 - 38 - ADAC/5500 Series User Manual 928
5.2.10.2 DAC DMA Transfer Mode
To overcome PCI interrupt inefficiencies, we have incorporated an on-board DMA engine analogous to the
older ISA type of DMA controller. The on-board DMA engine supports scatter/gather, also known as buffer
chaining, with a pair of address registers that point to the physical system memory to be used in the buffered
transfer. The DMA controller is loaded with the physical addresses of these buffers and only generates an
interrupt when the current transfer buffer process has been completed, thus further reducing the burden of
CPU interrupt intervention. This mode requires the least software overhead of the various PCI transfer
methods, and thus permits the highest potential conversion speeds. In this mode, DAC data is automatically
transferred from some predetermined physical memory location by the on-board DMA controller directly to
the DA FIFO. The DA FIFO data is then sent to the DAC holding register, where it is held and then output on
each DAC clock event. The pipeline continues to be maintained by automatic DMA actions until all samples
have been clocked out. The number of samples transferred in this manner is limited only by the amount of
system memory available. This mode can use any of the clocking methods, however, the overhead required for
software clocking may defeat the purpose of using DMA.
DMA Transfers will begin as soon as three conditions are met:
1. The DMA controller is programmed
2. The on-board DMA controller is enabled
3. Room exists in the DA FIFO.
Each DAC channel has its own FIFO register. The READY flag indicates when the DAC outputs have settled.
If the DACs are written to before their outputs have fully settled, the CERR flag will be immediately set
causing an interrupt if DMA is enabled.
The data written to the DACs may either be written as a two’s complement 16-bit word for bipolar
applications, or a 16-bit unsigned word when configured for unipolar operation.
There are a number of interrupts that are useful in DMA transfer mode. The Interrupt on DMATC is enabled
automatically when DMA is enabled. Essentially, an interrupt is sent when the DMA transfer is complete.
Another useful interrupt source is the DAC FIFO Underflow condition. If a DAC clock occurs and the D/A
FIFO is empty, the FERR flag sets, indicating a DAC underflow condition. Interrupt on DAC FIFO errors are
automatically enabled when using DMA.
If a clock or FIFO underflow error is generated during a DMA transfer, it is an indication that the PCI bus is
overloaded. Essentially this means that another board in the system is using up too much of the available bus
transfer bandwidth. If this is the case, concurrent bus accesses must be stopped, or the conversion frequency
must be slowed down.
Note: At power-up, both of the DACs are preloaded to output 0 volts.
5.2.11 Digital Acquisition
The ADAC/5500MF supports 16-bits of digital I/O and the ADAC/5501MF, ADAC/5502MF, ADAC/5503HR and
ADAC/5504HR Series boards support 48 bits of digital I/O. The first 16 bits on all boards are LSTTL compatible. The
32 additional bits on the ADAC/5501MF, ADAC/5502MF, ADAC/5503HR and ADAC/5504HR are both 3.3 V
CMOS and LSTTL compatible. All input ports are terminated to +5 V with 4.7 K
Ω resistors, and all output ports power
up driving low. The DIO ports operate with positive logic: A “0” represents a TTL low, and a “1” represents a TTL
high.