Measurement Computing ADAC/5500 Series - Manual (Page 40)

ADAC Series PCI Boards 795 - 35 - ADAC/5500 Series User Manual 928
5.2.5 ADC Clock and FIFO Errors
If the ADC is running in DMA operating modes, the board will automatically interrupt if the Clock Error Flag (CERR)
or FIFO Overflow Flag (FOVR) become active (i.e. set). These interrupt sources are automatically enabled when using
DMA.
5.2.6 ADC Data Transfer Modes
ADC data can be read directly from the on-board ADC FIFO register or directly to system memory via the on-board
DMA engine. The on-board FIFO data register requires 32-bit read access from the PCI bus. The FIFO register is used
in both POLLING and DMA transfer modes. The on-board DMA engine provides for the fastest means of collecting
ADC data by directly writing each conversion result to system memory. Two 32-bit DMA memory pointer registers
and two 16-bit memory sample count registers provide for continuous DMA transfers. Each 32-bit FIFO location may
contain two ADC samples or the upper 16-bits can contain the actual channel configuration settings for the current
sample. Since all ADAC PCI bus transfers are 32-bit operations, it is possible to transfer two analog data points into
memory during a single 32-bit transfer. This provides an immediate improvement in system bandwidth of a factor of
two when compared to 16-bit PCI implementations.
5.2.6.1 Software Polled ADC Acquisition Mode
This mode is the most CPU intensive acquisition mode. Basically, the ADC Channel Configuration RAM list,
clock and trigger modes are set up and initiated. The FIFO Not Empty signal is polled until data becomes
available. Once data becomes available, it is read from the ADC FIFO register.
5.2.6.2 ADC DMA Transfer Mode
To overcome PCI interrupt inefficiencies, the cards include an on-board DMA engine analogous to the older
ISA type of DMA controller. This on-board DMA engine supports scatter/gather, also known as buffer
chaining, with a pair of chain address registers that point to the physical system memory to be used in the
buffered transfer. The DMA controller is loaded with the physical addresses of these buffers, and only
generates interrupts once the current buffer transfer has been completed, thus reducing the burden of CPU
interrupt intervention. This PCI transfer mode requires the least software overhead, thus permitting the highest
potential conversion speeds. In this mode, ADC data is automatically transferred to some predetermined
physical memory location by the on-board DMA controller as soon as it becomes available. The number of
samples transferred in this manner is limited only by the amount of system memory available. This mode can
use any of the clocking methods, however, the overhead required for software clocking may defeat the
purpose of using DMA.
DMA transfers will begin as soon as three conditions are met:
1. The DMA controller is programmed
2. The on-board DMA controller is enabled
3. The ADC data becomes available.
There are a number of interrupts that are useful in DMA transfer mode. The Interrupt on DMATC event is
enabled automatically when DMA is enabled. Essentially, an interrupt is sent when the DMA transfer is
complete. Another useful interrupt is the Interrupt on Conversion Counter terminal count. This is used with
ABOUT Trigger Mode (see section 5.2.4.3 ADC External Trigger). Here the CPU is interrupted and the clock
is stopped when the on-board conversion counter reaches zero. Interrupt on conversion counter terminal count
is automatically enabled when using DMA.
If a clock or FIFO error is generated during a DMA transfer it is an indication that the PCI bus is overloaded.
Essentially this means that another board in the system is using up too much of the available bus transfer
bandwidth. If this is the case, concurrent bus accesses must be stopped, or the conversion frequency must be
slowed down.