Block diagram – Altera Cyclone II EP2C35 PCI Development Board User Manual
Page 9
Altera Corporation
Core Version a.b.c variable
1–3
May 2005
Cyclone II EP2C35 PCI Development Board Reference Manual
Introduction
Block Diagram
Figure 1–1
shows the board’s block diagram.
Figure 1–1. PCI Development Board, Cyclone II Edition Block Diagram
EP2C35F672
Cyclone II
Device
PCI Bus Switches
64-MByte DDR2
SDRAM Memory
Altera Daughter
Card (PROTO1)
Mictor Probe
Debug Connector
10/100 Ethernet
RS-232
JTAG Connector
High-Speed Clock Oscillator
Pushbutton Switches
DIP Switch Settings
User DIP switches
Jumpers
User LEDs
Status LEDs
Power
Regulators
External Power
Connector
Power LEDs
+3.3 V
+1.8 V
+1.2 V
PCI, PCI-X
Connector
Active Serial
Configuration
PCI Edge
Connector
+3.3V
Toggle
Switch
EPCS64 Safe Flash
Serial Programmer
EPCS64 User Flash
Serial Programmer
SMA Clock Connector
+16 V DC INPUT
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)