Altera Cyclone II EP2C35 PCI Development Board User Manual
Page 41
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Altera Corporation
Core Version 4.0.0
4–7
May 2005
Cyclone II EP2C35 PCI Development Board Reference Manual
Pin-Outs & Signal Specifications
DDR2_DQ7
-
F9
RN12.7
RN15.6
E15
DDR2_DQ8
-
C8
RN12.3
RN16.6
B16
DDR2_DQ9
-
C2
RN12.2
RN16.1
B15
DDR2_DQ10
-
D7
RN12.4
RN16.3
C15
DDR2_DQ11
-
D3
RN10.6
RN16.2
G13
DDR2_DQ12
-
D1
RN12.1
RN17.7
G14
DDR2_DQ13
-
D9
RN10.7
RN16.7
F14
DDR2_DQ14
-
B1
RN12.5
RN17.8
D14
DDR2_DQ15
-
B9
RN10.5
RN16.8
B11
DDR2_DQ16
G8
-
RN10.4
RN3.6
F11
DDR2_DQ17
G2
-
RN10.2
RN4.3
C9
DDR2_DQ18
H7
-
RN10.3
RN3.8
D9
DDR2_DQ19
H3
-
RN7.4
RN4.1
G10
DDR2_DQ20
H1
-
RN7.5
RN4.4
F10
DDR2_DQ21
H9
-
RN10.1
RN3.5
C8
DDR2_DQ22
F1
-
RN7.6
RN4.2
D8
DDR2_DQ23
F9
-
RN7.7
RN3.3
A7
DDR2_DQ24
C8
-
RN7.2
RN2.7
F12
DDR2_DQ25
C2
-
RN6.8
RN2.5
D12
DDR2_DQ26
D7
-
RN7.1
RN3.1
E12
DDR2_DQ27
D3
-
RN6.1
RN3.2
G11
DDR2_DQ28
D1
-
RN6.5
RN2.2
A10
DDR2_DQ29
D9
-
RN6.4
RN2.8
B10
DDR2_DQ30
B1
-
RN6.6
RN2.1
D10
DDR2_DQ31
B9
-
RN6.3
RN2.6
C10
Table 4–3. DDR2 SDRAM Memory & Terminator Signal Connections (Part 3 of 3)
DDR2 SDRAM
Signal
DDR2 SDRAM
Device 1 (U6)
DDR2 SDRAM
Device 2 (U10)
Non Fly-By
Terminator
Fly-By
Terminator
Cyclone II Pin
(U9)
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)