Altera Cyclone II EP2C35 PCI Development Board User Manual
Page 43

Altera Corporation
Core Version 4.0.0
4–9
May 2005
Cyclone II EP2C35 PCI Development Board Reference Manual
Pin-Outs & Signal Specifications
LAN_A2
–
U3.79
W1
LAN_A3
–
U3.80
W3
LAN_A4
–
U3.81
W6
LAN_A5
–
U3.82
Y1
LAN_A6
–
U3.83
Y3
LAN_A7
–
U3.84
Y4
LAN_A8
–
U3.85
Y5
LAN_A9
–
U3.86
P3
LAN_A10
–
U3.87
P4
LAN_A11
–
U3.88
R3
LAN_A12
–
U3.89
B2
LAN_A13
–
U3.90
J7
LAN_A14
–
U3.91
J8
LAN_A15
–
U3.92
L6
LAN_D0
–
U3.107
AA1
LAN_D1
–
U3.106
AA2
LAN_D2
–
U3.105
AA3
LAN_D3
–
U3.104
AA4
LAN_D4
–
U3.102
AA5
LAN_D5
–
U3.101
AB1
LAN_D6
–
U3.100
AB2
LAN_D7
–
U3.99
AB3
LAN_D8
–
U3.76
AB4
LAN_D9
–
U3.75
AC1
LAN_D10
–
U3.74
AC2
LAN_D11
–
U3.73
AC3
LAN_D12
–
U3.71
AD2
LAN_D13
–
U3.70
AD3
LAN_D14
–
U3.69
AE2
LAN_D15
–
U3.68
AE3
LAN_D16
–
U3.66
P6
LAN_D17
–
U3.65
P7
LAN_D18
–
U3.64
R2
Table 4–5. 10/100 Ethernet Interface Signal Connections (Part 2 of 3)
Ethernet Signal
Connector
Pin (RJ1)
MAC/PHY Pin (U3)
Cyclone II
Pin (U9)
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)