Push-button switches – Altera Cyclone II EP2C35 PCI Development Board User Manual
Page 48
4–14
Core Version 4.0.0
Altera Corporation
Cyclone II EP2C35 PCI Development Board Reference Manual
May 2005
Control & User Settings
Table 4–12
shows the user DIP switch bank (S4) signal names, board
references, and pin connections.
Push-Button Switches
Table 4–13
shows the push-button switch signal names and pin
connections.
Table 4–12. User DIP Switch Bank Settings
Board
Reference
User DIP Switch
Signal
Cyclone II Pin (U9)
0
Switch S4 Position 4
USER_SW0
AA12
1
Switch S4 Position 5
USER_SW1
AB8
2
Switch S4 Position 6
USER_SW2
AC6
3
Switch S4 Position 7
USER_SW3
AD12
4
Switch S4 Position 8
USER_SW4
AD8
Table 4–13. Push-Button Switch Signal Names & Pin Connections
Board Reference
Pin
Signal
Cyclone II Pin (U9)
RESET
S3.2
SYS_RESETn
C5
RECONFIG
S2.2
CONFIG_PBn
R23 (through diode U18)
PB0
S1.2
USER_PB0n
B12
PB1
S5.2
USER_PB1n
D13
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
- Remote Update IP Core (43 pages)
- Device-Specific Power Delivery Network (28 pages)
- Device-Specific Power Delivery Network (32 pages)
- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
- GPIO (22 pages)
- LVDS SERDES (27 pages)
- User Flash Memory (33 pages)
- ALTDQ_DQS2 (100 pages)
- Avalon Tri-State Conduit Components (18 pages)
- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
- Cyclone V Avalon-ST (248 pages)
- Stratix V Avalon-ST (286 pages)
- Stratix V Avalon-ST (293 pages)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP (10 pages)
- Arria 10 Avalon-ST (275 pages)
- Avalon Verification IP Suite (224 pages)
- Avalon Verification IP Suite (178 pages)
- FFT MegaCore Function (50 pages)
- DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP (140 pages)
- Floating-Point (157 pages)
- Integer Arithmetic IP (157 pages)
- Embedded Peripherals IP (336 pages)
- JESD204B IP (158 pages)
- Low Latency Ethernet 10G MAC (109 pages)
- LVDS SERDES Transmitter / Receiver (72 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (3 pages)
- Nios II Embedded Evaluation Kit Cyclone III Edition (80 pages)
- IP Compiler for PCI Express (372 pages)
- Parallel Flash Loader IP (57 pages)
- Nios II C2H Compiler (138 pages)
- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
- Phase-Locked Loop Reconfiguration IP Core (51 pages)
- DCFIFO (28 pages)