Altera Arria II GX FPGA Development Board, 6G Edition - Manual (Page 8)

1–4 Chapter 1: Overview
Development Board Block Diagram
Arria II GX FPGA Development Board, 6G Edition Reference Manual © July 2010 Altera Corporation
Development Board Block Diagram
Figure 1–1 shows the block diagram of the Arria II GX FPGA development board, 6G
Edition.
Handling the Board
When handling the board, it is important to observe the following static discharge
precaution:
c Without proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
Figure 1–1. Arria II GX FPGA Development Board, 6G Edition Block Diagram
Port B Port A
128 MB
DDR3 (x16)
2x16 LCD
Push-button
Switches
DIP Switch
LEDs
CPLD
64 MB
Flash
2 MB
SSRAM
x8 Edge
1 GB
DDR2 SODIMM (x64)
Gigabit Ethernet
PHY (RGMII)
Clock SMA OUT
Programmable Oscillator
100 M, 125 M, 156.25 M,
SMA (LVPECL)
Embedded
Blaster
USB
2.0
x120
x16
x1
x1 CLK IN
x1 REF CLK
x50
x11
x3
x4
x26 ADDR
XCVR x8 x8 Config
x76
CLKIN x3
CLKOUT x1
XCVR x4
x74
CLKIN x3
CLKOUT x3
XCVR x4
JTAG Chain
Programmable Oscillator
100 M, 125 M, 156.25 M,
x1 CLK IN
x3 REF CLK
x32 DATA
x1 REF CLK
EP2AGX260FF35
Z Z
x4
155.52 MHz