Altera Arria II GX FPGA Development Board, 6G Edition User Manual
Page 23
Chapter 2: Board Components
2–15
Configuration, Status, and Setup Elements
© July 2010 Altera Corporation
Arria II GX FPGA Development Board, 6G Edition Reference Manual
shows the flash memory map storage.
There are two pages reserved for the FPGA configuration data. The factory hardware
page is considered page 0 and is loaded upon power-up if the USER LOAD DIP switch
(SW4.4) is set to '1'. Otherwise, the user hardware page 1 is loaded. Pressing the load
image push-button switch (PB5) loads the FPGA with a hardware page based on
which CONFIG[2:0] LED (D11, D12, D13) is illuminated.
defines the
hardware page that loads when the load image push-button switch (PB5) is pressed.
Table 2–8. Flash Memory Map
Name
Size (Kbyte)
Address
Unused
32
0x03FF.FFFF
0x03FF.8000
32
0x03FF.7FFF
0x03FF.0000
32
0x03FE.FFFF
0x03FE.8000
32
0x03FE.7FFF
0x03FE.0000
User software
16,384
0x03FD.FFFF
0x0300.0000
Factory software
8,192
0x02FF.FFFF
0x0280.0000
zipfs—HTML, web content
8,192
0x027F.FFFF
0x0200.0000
User hardware 2
11,141
0x01FF.FFFF
0x0156.0000
User hardware 1
11,141
0x0155.FFFF
0x00AC.0000
Factory hardware
11,141
0x00AB.FFFF
0x0002.0000
PFL option bits
32
0x0001.FFFF
0x0001.8000
Board information
32
0x0001.7FFF
0x0001.0000
Ethernet option bits (MAC address)
32
0x0000.FFFF
0x0000.8000
User design reset vector
32
0x0000.7FFF
0x0000.0000